[PATCH] D111505: [X86] Prefer VEX encoding in X86 assembler.

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke added a comment.

In D111505#3054704 <https://reviews.llvm.org/D111505#3054704>, @craig.topper wrote:

> Did you consider other patches like this which will sort everything X86InstrAVX512.td after X86InstrSSE.td? The current sorting is done by the instruction name I think so VCVTSD2SIZrm_Int sorts before VCVTSD2SIrm_Int.
>
>   diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
>   index 00bdd127e3c2..aaf90aa13272 100644
>   --- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
>   +++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
>   @@ -636,7 +636,7 @@ struct MatchableInfo {
>        if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
>          return RequiredFeatures.size() > RHS.RequiredFeatures.size();
>    
>   -    return false;
>   +    return TheDef->getID() < RHS.TheDef->getID();
>      }
>    
>      /// couldMatchAmbiguouslyWith - Check whether this matchable could

Great. I once seek to reorder the matching table, but I didn't realize "TheDef->getID()" can achieve it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111505/new/

https://reviews.llvm.org/D111505