[PATCH] D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:3411
+
+  auto Or = N0.getOperand(0);
+  auto Shift = N0.getOperand(1);
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Please use SDValue. LLVM is pretty conservative about the use of auto. https://llvm.org/docs/CodingStandards.html#use-auto-type-deduction-to-make-code-more-readable


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Comment at: llvm/test/CodeGen/ARM/arm-icmp-shift-opt.ll:118
+; Negative test: optimization should not be applied as
+; constants used in shifts does not match.
+define i1 @opt_setcc_expanded_shl_wrong_shifts(i32 %a, i32 %b) {
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"does not match" -> "do not match" since constants is plural.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111530/new/

https://reviews.llvm.org/D111530