[PATCH] D111530: [TargetLowering] Optimize expanded SRL/SHL feeded into SETCC ne/eq 0

[Filipp Zhinkin via Phabricator via llvm-commits]

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During legalization SHL/SRL nodes could be expanded into expression
that rotates low/high part of original input and then apply OR to
rotated part and other part. If the result of this operation is
compared for equality/not-equality with zero then rotation could
be removed as it does not affect comparision result.

Bug report: https://bugs.llvm.org/show_bug.cgi?id=50197


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111530

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/arm64-icmp-shift-opt.ll
  llvm/test/CodeGen/ARM/arm-icmp-shift-opt.ll
  llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
  llvm/test/CodeGen/X86/icmp-shift-opt.ll

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