[PATCH] D110579: [AMDGPU] Add two new intrinsics to control fp_trunc rounding mode

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIModeRegister.cpp:439
+      // Build a MI to do the conversion
+      BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CVT_F16_F32_e64), Dest.getReg())
+          .addImm(0)
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If you arrange for the pseudo to have exactly the same operands as the real instruction, then you don't need to build or delete instructions, all you need to do is change the opcode, which you can do with MI.setDesc().


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Comment at: llvm/lib/Target/AMDGPU/SIModeRegister.cpp:479
+  // Select some pseudo-instructions that need a special mode
+  for (MachineBasicBlock &BB : MF)
+    selectModePseudos(BB, TII);
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I'm not sure this needs another pass over all instructions in the function. Would it be cleaner to do it in phase 1? Maybe even inside getInstructionMode???


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  https://reviews.llvm.org/D110579/new/

https://reviews.llvm.org/D110579