[PATCH] D111497: m68k: Support bit shifts on 64-bit integers
Min-Yih Hsu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 9 21:49:20 PDT 2021
myhsu added inline comments.
================
Comment at: llvm/lib/Target/M68k/M68kISelLowering.cpp:104
+ for (auto OP : {ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS}) {
+ setOperationAction(OP, MVT::i32, Custom);
----------------
Please remove curly brace if there is only one statement in for-loop.
================
Comment at: llvm/lib/Target/M68k/M68kISelLowering.cpp:380
-SDValue
-M68kTargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
- const SmallVectorImpl<ISD::InputArg> &Ins,
- const SDLoc &DL, SelectionDAG &DAG,
- const CCValAssign &VA,
- MachineFrameInfo &MFI,
- unsigned ArgIdx) const {
+SDValue M68kTargetLowering::LowerMemArgument(
+ SDValue Chain, CallingConv::ID CallConv,
----------------
I feel like this is modified by clang-format. Can you format //only// the part you changed using `clang/tools/clang-format/clang-format-diff.py`
================
Comment at: llvm/lib/Target/M68k/M68kISelLowering.cpp:3357
SDValue Carry = CCR.getOperand(0);
- while (Carry.getOpcode() == ISD::TRUNCATE ||
- Carry.getOpcode() == ISD::ZERO_EXTEND ||
- Carry.getOpcode() == ISD::SIGN_EXTEND ||
- Carry.getOpcode() == ISD::ANY_EXTEND ||
- (Carry.getOpcode() == ISD::AND &&
- isOneConstant(Carry.getOperand(1))))
+ while (
+ Carry.getOpcode() == ISD::TRUNCATE ||
----------------
AnnikaCodes wrote:
> These other changes are because I ran `clang-format` on the file; it's syntactically the same.
ditto, please use clang-format-diff.py instead
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D111497/new/
https://reviews.llvm.org/D111497
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