[PATCH] D111497: m68k: Support bit shifts on 64-bit integers

[Annika L. via Phabricator via llvm-commits]

AnnikaCodes updated this revision to Diff 378465.
AnnikaCodes added a comment.

Regenerate CHECKs


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111497/new/

https://reviews.llvm.org/D111497

Files:
  llvm/lib/Target/M68k/M68kISelLowering.cpp
  llvm/test/CodeGen/M68k/Arith/bitwise.ll


Index: llvm/test/CodeGen/M68k/Arith/bitwise.ll
===================================================================
--- llvm/test/CodeGen/M68k/Arith/bitwise.ll
+++ llvm/test/CodeGen/M68k/Arith/bitwise.ll
@@ -230,3 +230,45 @@
   %1 = xor i32 %a, 305419896
   ret i32 %1
 }
+
+define i64 @lshr64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: lshr64:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    suba.l #12, %sp
+; CHECK-NEXT:    move.l (28,%sp), (8,%sp)
+; CHECK-NEXT:    move.l (20,%sp), (4,%sp)
+; CHECK-NEXT:    move.l (16,%sp), (%sp)
+; CHECK-NEXT:    jsr __lshrdi3 at PLT
+; CHECK-NEXT:    adda.l #12, %sp
+; CHECK-NEXT:    rts
+  %1 = lshr i64 %a, %b
+  ret i64 %1
+}
+
+define i64 @ashr64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: ashr64:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    suba.l #12, %sp
+; CHECK-NEXT:    move.l (28,%sp), (8,%sp)
+; CHECK-NEXT:    move.l (20,%sp), (4,%sp)
+; CHECK-NEXT:    move.l (16,%sp), (%sp)
+; CHECK-NEXT:    jsr __ashrdi3 at PLT
+; CHECK-NEXT:    adda.l #12, %sp
+; CHECK-NEXT:    rts
+  %1 = ashr i64 %a, %b
+  ret i64 %1
+}
+
+define i64 @shl64(i64 %a, i64 %b) nounwind {
+; CHECK-LABEL: shl64:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    suba.l #12, %sp
+; CHECK-NEXT:    move.l (28,%sp), (8,%sp)
+; CHECK-NEXT:    move.l (20,%sp), (4,%sp)
+; CHECK-NEXT:    move.l (16,%sp), (%sp)
+; CHECK-NEXT:    jsr __ashldi3 at PLT
+; CHECK-NEXT:    adda.l #12, %sp
+; CHECK-NEXT:    rts
+  %1 = shl i64 %a, %b
+  ret i64 %1
+}
Index: llvm/lib/Target/M68k/M68kISelLowering.cpp
===================================================================
--- llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -101,6 +101,10 @@
     setOperationAction(OP, MVT::i32, Expand);
   }
 
+  for (auto OP : {ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS}) {
+    setOperationAction(OP, MVT::i32, Expand);
+  }
+
   // Add/Sub overflow ops with MVT::Glues are lowered to CCR dependences.
   for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
     setOperationAction(ISD::ADDC, VT, Custom);


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