[PATCH] D111497: m68k: Support bit shifts on 64-bit integers
Annika L. via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Oct 9 10:25:27 PDT 2021
AnnikaCodes created this revision.
AnnikaCodes added reviewers: myhsu, jrtc27.
Herald added a subscriber: hiraditya.
AnnikaCodes requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
As per https://bugs.llvm.org/show_bug.cgi?id=52119.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D111497
Files:
llvm/lib/Target/M68k/M68kISelLowering.cpp
llvm/test/CodeGen/M68k/Arith/bitwise.ll
Index: llvm/test/CodeGen/M68k/Arith/bitwise.ll
===================================================================
--- llvm/test/CodeGen/M68k/Arith/bitwise.ll
+++ llvm/test/CodeGen/M68k/Arith/bitwise.ll
@@ -230,3 +230,18 @@
%1 = xor i32 %a, 305419896
ret i32 %1
}
+
+define i64 @lshr64(i64 %a, i64 %b) nounwind {
+ %1 = lshr i64 %a, %b
+ ret i64 %1
+}
+
+define i64 @ashr64(i64 %a, i64 %b) nounwind {
+ %1 = ashr i64 %a, %b
+ ret i64 %1
+}
+
+define i64 @shl64(i64 %a, i64 %b) nounwind {
+ %1 = shl i64 %a, %b
+ ret i64 %1
+}
Index: llvm/lib/Target/M68k/M68kISelLowering.cpp
===================================================================
--- llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -101,6 +101,10 @@
setOperationAction(OP, MVT::i32, Expand);
}
+ for (auto OP : {ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS}) {
+ setOperationAction(OP, MVT::i32, Expand);
+ }
+
// Add/Sub overflow ops with MVT::Glues are lowered to CCR dependences.
for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
setOperationAction(ISD::ADDC, VT, Custom);
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D111497.378461.patch
Type: text/x-patch
Size: 1121 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20211009/751860fc/attachment.bin>
More information about the llvm-commits
mailing list