[PATCH] D110830: [AArch64] Make -mcpu=generic schedule for an in-order core

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sat Oct 9 07:58:56 PDT 2021


This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGadec92236164: [AArch64] Make -mcpu=generic schedule for an in-order core (authored by dmgreen).

Changed prior to commit:
  https://reviews.llvm.org/D110830?vs=377240&id=378452#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110830/new/

https://reviews.llvm.org/D110830

Files:
  llvm/lib/Target/AArch64/AArch64.td
  llvm/test/Analysis/CostModel/AArch64/shuffle-select.ll
  llvm/test/Analysis/CostModel/AArch64/vector-select.ll
  llvm/test/CodeGen/AArch64/DAGCombine_vscale.ll
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
  llvm/test/CodeGen/AArch64/GlobalISel/byval-call.ll
  llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll
  llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
  llvm/test/CodeGen/AArch64/GlobalISel/merge-stores-truncating.ll
  llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
  llvm/test/CodeGen/AArch64/aarch64-addv.ll
  llvm/test/CodeGen/AArch64/aarch64-be-bv.ll
  llvm/test/CodeGen/AArch64/aarch64-dup-ext-scalable.ll
  llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
  llvm/test/CodeGen/AArch64/aarch64-fold-lslfast.ll
  llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
  llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
  llvm/test/CodeGen/AArch64/aarch64-smull.ll
  llvm/test/CodeGen/AArch64/aarch64-tail-dup-size.ll
  llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll
  llvm/test/CodeGen/AArch64/addimm-mulimm.ll
  llvm/test/CodeGen/AArch64/addsub-constant-folding.ll
  llvm/test/CodeGen/AArch64/addsub.ll
  llvm/test/CodeGen/AArch64/align-down.ll
  llvm/test/CodeGen/AArch64/and-mask-removal.ll
  llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll
  llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
  llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
  llvm/test/CodeGen/AArch64/arm64-addrmode.ll
  llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
  llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
  llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll
  llvm/test/CodeGen/AArch64/arm64-csel.ll
  llvm/test/CodeGen/AArch64/arm64-dup.ll
  llvm/test/CodeGen/AArch64/arm64-fcopysign.ll
  llvm/test/CodeGen/AArch64/arm64-fmadd.ll
  llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll
  llvm/test/CodeGen/AArch64/arm64-indexed-memory.ll
  llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
  llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
  llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll
  llvm/test/CodeGen/AArch64/arm64-ldp.ll
  llvm/test/CodeGen/AArch64/arm64-memset-inline.ll
  llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
  llvm/test/CodeGen/AArch64/arm64-neon-aba-abd.ll
  llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
  llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll
  llvm/test/CodeGen/AArch64/arm64-nvcast.ll
  llvm/test/CodeGen/AArch64/arm64-popcnt.ll
  llvm/test/CodeGen/AArch64/arm64-promote-const-complex-initializers.ll
  llvm/test/CodeGen/AArch64/arm64-register-pairing.ll
  llvm/test/CodeGen/AArch64/arm64-rev.ll
  llvm/test/CodeGen/AArch64/arm64-setcc-int-to-fp-combine.ll
  llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
  llvm/test/CodeGen/AArch64/arm64-sli-sri-opt.ll
  llvm/test/CodeGen/AArch64/arm64-srl-and.ll
  llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
  llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll
  llvm/test/CodeGen/AArch64/arm64-tls-local-exec.ll
  llvm/test/CodeGen/AArch64/arm64-trunc-store.ll
  llvm/test/CodeGen/AArch64/arm64-vabs.ll
  llvm/test/CodeGen/AArch64/arm64-vhadd.ll
  llvm/test/CodeGen/AArch64/arm64-vmul.ll
  llvm/test/CodeGen/AArch64/arm64-windows-calls.ll
  llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
  llvm/test/CodeGen/AArch64/arm64_32-addrs.ll
  llvm/test/CodeGen/AArch64/arm64_32-atomics.ll
  llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
  llvm/test/CodeGen/AArch64/atomic-ops-not-barriers.ll
  llvm/test/CodeGen/AArch64/bcmp-inline-small.ll
  llvm/test/CodeGen/AArch64/bitcast-promote-widen.ll
  llvm/test/CodeGen/AArch64/bitfield-insert.ll
  llvm/test/CodeGen/AArch64/build-one-lane.ll
  llvm/test/CodeGen/AArch64/build-vector-extract.ll
  llvm/test/CodeGen/AArch64/cgp-usubo.ll
  llvm/test/CodeGen/AArch64/cmp-select-sign.ll
  llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll
  llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
  llvm/test/CodeGen/AArch64/cond-sel-value-prop.ll
  llvm/test/CodeGen/AArch64/consthoist-gep.ll
  llvm/test/CodeGen/AArch64/csr-split.ll
  llvm/test/CodeGen/AArch64/ctpop-nonean.ll
  llvm/test/CodeGen/AArch64/dag-combine-select.ll
  llvm/test/CodeGen/AArch64/dag-combine-trunc-build-vec.ll
  llvm/test/CodeGen/AArch64/dag-numsignbits.ll
  llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-signed.ll
  llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-unsigned.ll
  llvm/test/CodeGen/AArch64/emutls.ll
  llvm/test/CodeGen/AArch64/expand-select.ll
  llvm/test/CodeGen/AArch64/expand-vector-rot.ll
  llvm/test/CodeGen/AArch64/extract-bits.ll
  llvm/test/CodeGen/AArch64/extract-lowbits.ll
  llvm/test/CodeGen/AArch64/f16-instructions.ll
  llvm/test/CodeGen/AArch64/fabs.ll
  llvm/test/CodeGen/AArch64/fadd-combines.ll
  llvm/test/CodeGen/AArch64/faddp-half.ll
  llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
  llvm/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll
  llvm/test/CodeGen/AArch64/fast-isel-gep.ll
  llvm/test/CodeGen/AArch64/fast-isel-memcpy.ll
  llvm/test/CodeGen/AArch64/fast-isel-shift.ll
  llvm/test/CodeGen/AArch64/fdiv_combine.ll
  llvm/test/CodeGen/AArch64/fold-global-offsets.ll
  llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
  llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll
  llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
  llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
  llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
  llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
  llvm/test/CodeGen/AArch64/framelayout-frame-record.mir
  llvm/test/CodeGen/AArch64/framelayout-unaligned-fp.ll
  llvm/test/CodeGen/AArch64/func-calls.ll
  llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
  llvm/test/CodeGen/AArch64/funnel-shift.ll
  llvm/test/CodeGen/AArch64/global-merge-3.ll
  llvm/test/CodeGen/AArch64/half.ll
  llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
  llvm/test/CodeGen/AArch64/hwasan-check-memaccess.ll
  llvm/test/CodeGen/AArch64/i128_volatile_load_store.ll
  llvm/test/CodeGen/AArch64/implicit-null-check.ll
  llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
  llvm/test/CodeGen/AArch64/isinf.ll
  llvm/test/CodeGen/AArch64/known-never-nan.ll
  llvm/test/CodeGen/AArch64/ldst-opt.ll
  llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
  llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
  llvm/test/CodeGen/AArch64/lowerMUL-newload.ll
  llvm/test/CodeGen/AArch64/machine-licm-sink-instr.ll
  llvm/test/CodeGen/AArch64/machine-outliner-throw.ll
  llvm/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll
  llvm/test/CodeGen/AArch64/madd-lohi.ll
  llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll
  llvm/test/CodeGen/AArch64/merge-trunc-store.ll
  llvm/test/CodeGen/AArch64/midpoint-int.ll
  llvm/test/CodeGen/AArch64/min-max.ll
  llvm/test/CodeGen/AArch64/minmax-of-minmax.ll
  llvm/test/CodeGen/AArch64/minmax.ll
  llvm/test/CodeGen/AArch64/misched-fusion-lit.ll
  llvm/test/CodeGen/AArch64/misched-fusion.ll
  llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
  llvm/test/CodeGen/AArch64/neg-abs.ll
  llvm/test/CodeGen/AArch64/neg-imm.ll
  llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
  llvm/test/CodeGen/AArch64/neon-dotpattern.ll
  llvm/test/CodeGen/AArch64/neon-dotreduce.ll
  llvm/test/CodeGen/AArch64/neon-mla-mls.ll
  llvm/test/CodeGen/AArch64/neon-mov.ll
  llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll
  llvm/test/CodeGen/AArch64/neon-shift-neg.ll
  llvm/test/CodeGen/AArch64/neon-truncstore.ll
  llvm/test/CodeGen/AArch64/nontemporal.ll
  llvm/test/CodeGen/AArch64/overeager_mla_fusing.ll
  llvm/test/CodeGen/AArch64/pow.ll
  llvm/test/CodeGen/AArch64/pull-conditional-binop-through-shift.ll
  llvm/test/CodeGen/AArch64/qmovn.ll
  llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
  llvm/test/CodeGen/AArch64/rand.ll
  llvm/test/CodeGen/AArch64/reduce-and.ll
  llvm/test/CodeGen/AArch64/reduce-or.ll
  llvm/test/CodeGen/AArch64/reduce-xor.ll
  llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll
  llvm/test/CodeGen/AArch64/rotate-extract.ll
  llvm/test/CodeGen/AArch64/rvmarker-pseudo-expansion-and-outlining.mir
  llvm/test/CodeGen/AArch64/sadd_sat.ll
  llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
  llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/sat-add.ll
  llvm/test/CodeGen/AArch64/sdivpow2.ll
  llvm/test/CodeGen/AArch64/seh-finally.ll
  llvm/test/CodeGen/AArch64/select-with-and-or.ll
  llvm/test/CodeGen/AArch64/select_const.ll
  llvm/test/CodeGen/AArch64/select_fmf.ll
  llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
  llvm/test/CodeGen/AArch64/settag-merge-order.ll
  llvm/test/CodeGen/AArch64/settag-merge.ll
  llvm/test/CodeGen/AArch64/settag.ll
  llvm/test/CodeGen/AArch64/shift-amount-mod.ll
  llvm/test/CodeGen/AArch64/shift-by-signext.ll
  llvm/test/CodeGen/AArch64/shift-mod.ll
  llvm/test/CodeGen/AArch64/shrink-wrapping-vla.ll
  llvm/test/CodeGen/AArch64/sibling-call.ll
  llvm/test/CodeGen/AArch64/signbit-shift.ll
  llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
  llvm/test/CodeGen/AArch64/sitofp-fixed-legal.ll
  llvm/test/CodeGen/AArch64/speculation-hardening-loads.ll
  llvm/test/CodeGen/AArch64/speculation-hardening.mir
  llvm/test/CodeGen/AArch64/split-vector-insert.ll
  llvm/test/CodeGen/AArch64/sqrt-fastmath.ll
  llvm/test/CodeGen/AArch64/srem-lkk.ll
  llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll
  llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
  llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
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  llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
  llvm/test/CodeGen/AArch64/ssub_sat.ll
  llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
  llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
  llvm/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll
  llvm/test/CodeGen/AArch64/stack-guard-sysreg.ll
  llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll
  llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
  llvm/test/CodeGen/AArch64/sve-expand-div.ll
  llvm/test/CodeGen/AArch64/sve-extract-element.ll
  llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
  llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
  llvm/test/CodeGen/AArch64/sve-fcopysign.ll
  llvm/test/CodeGen/AArch64/sve-fcvt.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-extract-vector-elt.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-float-compares.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-immediates.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll
  llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
  llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll
  llvm/test/CodeGen/AArch64/sve-gep.ll
  llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
  llvm/test/CodeGen/AArch64/sve-insert-element.ll
  llvm/test/CodeGen/AArch64/sve-insert-vector.ll
  llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll
  llvm/test/CodeGen/AArch64/sve-int-arith.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith.ll
  llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
  llvm/test/CodeGen/AArch64/sve-ld1r.ll
  llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll
  llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll
  llvm/test/CodeGen/AArch64/sve-masked-scatter-legalize.ll
  llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
  llvm/test/CodeGen/AArch64/sve-pred-arith.ll
  llvm/test/CodeGen/AArch64/sve-sext-zext.ll
  llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
  llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
  (69 more files...)



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