[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[Shao-Ce Sun via Phabricator via llvm-commits]

achieveartificialintelligence added a comment.

In D93298#3020917 <https://reviews.llvm.org/D93298#3020917>, @frasercrmck wrote:

> In D93298#3014160 <https://reviews.llvm.org/D93298#3014160>, @jrtc27 wrote:
>
>> The amount of duplication here really depresses me and is only going to get worse once codegen is added, but TableGen isn't able to have operands that use different register classes based on even HwMode, that I know of, and whilst you could make use of multi classes to generate both versions of the instructions you can't easily do that for patterns, so I don't know what the right answer is.
>
> Do we know if it's possible to teach TableGen how to do that? This extension seems like a good reason to implement such a feature as the duplication really is unfortunate.
>
> I thought that `MCOperandInfo` may be an issue but there's already dynamic lookup there to support `isLookupPtrRegClass`.

@frasercrmck Thank you for your guidance. I don't quite understand what is the role of `isLookupPtrRegClass` here, or how to use `isLookupPtrRegClass`? Could you please give me more detailed instructions?


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