[llvm] 17b89f9 - [GlobalISel] Improve G_UMHULH -> LSHR combine to accept non-uniform constant vectors.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2021-10-08T11:25:26-07:00
New Revision: 17b89f9daad56f80c29b46bed0b6ce94093dcfc9

URL: https://github.com/llvm/llvm-project/commit/17b89f9daad56f80c29b46bed0b6ce94093dcfc9
DIFF: https://github.com/llvm/llvm-project/commit/17b89f9daad56f80c29b46bed0b6ce94093dcfc9.diff

LOG: [GlobalISel] Improve G_UMHULH -> LSHR combine to accept non-uniform constant vectors.

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/combine-umulh-to-lshr.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index b610047cbf3ec..f5a104e8adcd0 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -4595,8 +4595,12 @@ bool CombinerHelper::matchUMulHToLShr(MachineInstr &MI) {
   Register Dst = MI.getOperand(0).getReg();
   LLT Ty = MRI.getType(Dst);
   LLT ShiftAmtTy = getTargetLowering().getPreferredShiftAmountTy(Ty);
-  auto CstVal = isConstantOrConstantSplatVector(*MRI.getVRegDef(RHS), MRI);
-  if (!CstVal || CstVal->isOne() || !isPowerOf2_64(CstVal->getZExtValue()))
+  auto MatchPow2ExceptOne = [&](const Constant *C) {
+    if (auto *CI = dyn_cast<ConstantInt>(C))
+      return CI->getValue().isPowerOf2() && !CI->getValue().isOne();
+    return false;
+  };
+  if (!matchUnaryPredicate(MRI, RHS, MatchPow2ExceptOne, false))
     return false;
   return isLegalOrBeforeLegalizer({TargetOpcode::G_LSHR, {Ty, ShiftAmtTy}});
 }

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-umulh-to-lshr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-umulh-to-lshr.mir
index e5578801ce255..d5fe354719908 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-umulh-to-lshr.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-umulh-to-lshr.mir
@@ -99,3 +99,69 @@ body:             |
     %2:_(s64) = G_UMULH %0, %1(s64)
     $x0 = COPY %2(s64)
 ...
+---
+name:            mul_to_lshr_vector_nonuniform_const
+alignment:       4
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $q0
+    ; CHECK-LABEL: name: mul_to_lshr_vector_nonuniform_const
+    ; CHECK: liveins: $q0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+    ; CHECK-NEXT: %cst3:_(s32) = G_CONSTANT i32 32
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 27
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 26
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32)
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C4]](s32), [[C4]](s32), [[C4]](s32), [[C4]](s32)
+    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
+    ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR %cst3(s32), %cst3(s32), %cst3(s32), %cst3(s32)
+    ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(<4 x s32>) = G_SUB [[BUILD_VECTOR2]], [[SUB]]
+    ; CHECK-NEXT: %mulh:_(<4 x s32>) = G_LSHR [[COPY]], [[SUB1]](<4 x s32>)
+    ; CHECK-NEXT: $q0 = COPY %mulh(<4 x s32>)
+    %0:_(<4 x s32>) = COPY $q0
+    %cst1:_(s32) = G_CONSTANT i32 8
+    %cst2:_(s32) = G_CONSTANT i32 16
+    %cst3:_(s32) = G_CONSTANT i32 32
+    %cst4:_(s32) = G_CONSTANT i32 64
+    %bv:_(<4 x s32>) = G_BUILD_VECTOR %cst1, %cst2, %cst3, %cst4
+    %mulh:_(<4 x s32>) = G_UMULH %0, %bv(<4 x s32>)
+    $q0 = COPY %mulh(<4 x s32>)
+...
+---
+name:            mul_to_lshr_vector_nonuniform_const_elt_is_one
+alignment:       4
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+    liveins: $q0
+    ; CHECK-LABEL: name: mul_to_lshr_vector_nonuniform_const_elt_is_one
+    ; CHECK: liveins: $q0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+    ; CHECK-NEXT: %cst1:_(s32) = G_CONSTANT i32 8
+    ; CHECK-NEXT: %cst2:_(s32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: %cst3:_(s32) = G_CONSTANT i32 32
+    ; CHECK-NEXT: %cst4:_(s32) = G_CONSTANT i32 64
+    ; CHECK-NEXT: %bv:_(<4 x s32>) = G_BUILD_VECTOR %cst1(s32), %cst2(s32), %cst3(s32), %cst4(s32)
+    ; CHECK-NEXT: %mulh:_(<4 x s32>) = G_UMULH [[COPY]], %bv
+    ; CHECK-NEXT: $q0 = COPY %mulh(<4 x s32>)
+    %0:_(<4 x s32>) = COPY $q0
+    %cst1:_(s32) = G_CONSTANT i32 8
+    %cst2:_(s32) = G_CONSTANT i32 1
+    %cst3:_(s32) = G_CONSTANT i32 32
+    %cst4:_(s32) = G_CONSTANT i32 64
+    %bv:_(<4 x s32>) = G_BUILD_VECTOR %cst1, %cst2, %cst3, %cst4
+    %mulh:_(<4 x s32>) = G_UMULH %0, %bv(<4 x s32>)
+    $q0 = COPY %mulh(<4 x s32>)
+...