[PATCH] D92132: [LV] Support widened induction variables in epilogue vectorization.

[Venkataramanan Kumar via Phabricator via llvm-commits]

venkataramanan.kumar.llvm added a comment.

Hi Florian,

This patch breaks one assert when building compiler-rt.   However I noticed  that in my work space I lowered the epilog generation thresholds to 8 so got this assert.

Here is the general reproducer.

---Snip winden-ce.cpp ---
unsigned short int *  MemToShadow(unsigned int  x);

void Add( unsigned int begin,unsigned int end, unsigned int cfi_check) {

  // Don't fill anything below cfi_check. We can not represent those addresses
  // in the shadow, and must make sure at codegen to place all valid call
  // targets above cfi_check.
  //begin = Max(begin, cfi_check);
  unsigned short int *s = MemToShadow(begin);
  unsigned short int *s_end = MemToShadow(end - 1) + 1;
  unsigned short int  sv = ((begin - cfi_check)) + 1;
  for (; s < s_end; s++, sv++)
    *s = sv;

}
---Snip--

clang++ -O3  winden-ce.cpp   -S -emit-llvm  -mllvm -epilogue-vectorization-minimum-VF=8

LoopVectorize.cpp:2535: virtual llvm::Value* llvm::InnerLoopVectorizer::getStepVector(llvm::Value*, int, llvm::Value*, llvm::Instruction::BinaryOps): Assertion `Step->getType() == STy && "Step has wrong type"' failed.

I noticed Main loop Vector splat created in the preheader is with 16 type (unsigned short *) 
%.splat = shufflevector <8 x i16> %.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer

whereas Epilog loop creates vector splat is created with i32 type. 
 %.splat31 = shufflevector <4 x i64> %.splatinsert30, <4 x i64> poison, <4 x i32> zeroinitializer


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D92132/new/

https://reviews.llvm.org/D92132