[PATCH] D111304: [RISCV] Reorder the vector register allocation order.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:506
+             (add V8M2, V10M2, V12M2, V14M2, V16M2, V18M2, V20M2, V22M2,
+                  V24M2, V26M2, V28M2, V30M2, V0M2, V2M2, V4M2, V6M2), 2>;
 
----------------
https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Target/Target.td#L329

Seems like sequence have optional 4th argument for stride, so this could be simplified to
```
               (add (sequence "V%uM2", 8, 31, 2),
                    (sequence "V%uM2", 0, 7, 2)), 2>;
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111304/new/

https://reviews.llvm.org/D111304