[PATCH] D109963: [AArch64] Split bitmask immediate of bitwise AND operation

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 updated this revision to Diff 377994.
jaykang10 added a comment.

Fixed a bug

- For the 32 bit form of instruction, the upper 32 bits of the destination register are set to zero. If there is SUBREG_TO_REG, set the upper 32 bits of `UImm` to zero.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109963/new/

https://reviews.llvm.org/D109963

Files:
  llvm/lib/Target/AArch64/AArch64.h
  llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
  llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
  llvm/lib/Target/AArch64/CMakeLists.txt
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
  llvm/test/CodeGen/AArch64/O3-pipeline.ll
  llvm/test/CodeGen/AArch64/aarch64-split-and-bitmask-immediate.ll
  llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-innerouter.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D109963.377994.patch
Type: text/x-patch
Size: 21436 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20211007/caa2058c/attachment.bin>