[PATCH] D111165: [AArch64][SVE] Add fixed type lowering for EXTRACT_SUBVECTOR

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10684
 
+  if (useSVEForFixedLengthVectorVT(InVT)) {
+    SDLoc DL(Op);
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Is it worth moving this block after the special cases below?  I'm just think if there's a time when useSVEForFixedLengthVectorVT accepts 128bit or smaller vectors.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10692
+    SDValue Splice = DAG.getNode(ISD::VECTOR_SPLICE, DL, ContainerVT, NewInVec,
+                                 DAG.getUNDEF(ContainerVT),
+                                 DAG.getConstant(Idx, DL, MVT::i64));
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Can you use `NewInVec` here as `UNDEF` could create a false dependency that hurts performance.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16845-16846
+  // Avoid creating a splat of zero by extending an undef
+  if (N->getOperand(1).isUndef())
+    RHS = DAG.getUNDEF(ExtIntTy);
+  else
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To me this looks like we're missing a trivial fold within getNode for either `BITCAST` or whatever `DAG.getAnyExtOrTrunc` creates?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111165/new/

https://reviews.llvm.org/D111165