[PATCH] D111325: RFC: Use data deps for schedule barrier; Only look at data deps in MacroFusion

Matthias Braun via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 7 10:21:47 PDT 2021


MatzeB created this revision.
MatzeB added a reviewer: dmgreen.
Herald added subscribers: wenlei, pengfei, hiraditya, mcrosier.
MatzeB requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

ScheduleDAGInstrs used to use artifical edges between the barrier instruction and its predecessor instead. While this makes sense for live-out values that aren't actually used right away I don't see a good reason to do that for the uses in the instruction itself. This changes the code to use Data dependencies.

It also changes MacroFusion code to exclusively look at data dependencies.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111325

Files:
  llvm/lib/CodeGen/MacroFusion.cpp
  llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll
  llvm/test/CodeGen/AArch64/GlobalISel/select-bitfield-insert.ll
  llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll
  llvm/test/CodeGen/AArch64/addsub.ll
  llvm/test/CodeGen/AArch64/align-down.ll
  llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll
  llvm/test/CodeGen/AArch64/arm64-memset-inline.ll
  llvm/test/CodeGen/AArch64/branch-relax-alignment.ll
  llvm/test/CodeGen/AArch64/branch-relax-asm.ll
  llvm/test/CodeGen/AArch64/branch-relax-bcc.ll
  llvm/test/CodeGen/AArch64/cgp-usubo.ll
  llvm/test/CodeGen/AArch64/cmp-select-sign.ll
  llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
  llvm/test/CodeGen/AArch64/fadd-combines.ll
  llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
  llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
  llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
  llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
  llvm/test/CodeGen/AArch64/merge-store-dependency.ll
  llvm/test/CodeGen/AArch64/misched-fusion.ll
  llvm/test/CodeGen/AArch64/nontemporal.ll
  llvm/test/CodeGen/AArch64/pow.ll
  llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll
  llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
  llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
  llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-innerouter.ll
  llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-interleavedbits.ll
  llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
  llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-lowhigh.ll
  llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-variablemask.ll
  llvm/test/CodeGen/AArch64/vec-libcalls.ll
  llvm/test/CodeGen/AArch64/vec_uaddo.ll
  llvm/test/CodeGen/AArch64/vec_umulo.ll
  llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization-strict.ll
  llvm/test/CodeGen/X86/atomic-idempotent.ll
  llvm/test/CodeGen/X86/critical-anti-dep-breaker.ll
  llvm/test/CodeGen/X86/tail-opts.ll

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