[PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added a comment.

In D110250#3047339 <https://reviews.llvm.org/D110250#3047339>, @HsiangKai wrote:

> I am preparing another patch to reorder the allocation order as v8 to v23, v24 to v31, and v0 to v7. I am not sure if it is better or not. Just refer to GPR that it uses argument registers as the first priority allocation registers. I already forgot why the vector register allocation order starts from v25.

https://reviews.llvm.org/D111304


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https://reviews.llvm.org/D110250