[PATCH] D111258: [PowerPC] Emit dcbt and dcbtst in place of their extended mnemonics on AIX

[Albion Fung via Phabricator via llvm-commits]

Conanap created this revision.
Conanap added reviewers: nemanjai, jsji, PowerPC.
Conanap added projects: clang, LLVM, PowerPC.
Herald added subscribers: kbarton, hiraditya.
Conanap requested review of this revision.

On AIX, the system assembler does not support the extended mnemonics
`dcbtt` and `dcbtstt`. This patch stops them from being emitted on
AIX and emits the base mnemonics instead, `dcbt X, X, 16` and
`dcbtstt X, X, 16` respectively.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111258

Files:
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
@@ -26,14 +26,14 @@
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:    lwz 3, 0(3)
-; CHECK-AIX-NEXT:    dcbtstt 0, 3
+; CHECK-AIX-NEXT:    dcbtst 0, 3, 16
 ; CHECK-AIX-NEXT:    blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtstt:
 ; CHECK-AIX64:       # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:    ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:    ld 3, 0(3)
-; CHECK-AIX64-NEXT:    dcbtstt 0, 3
+; CHECK-AIX64-NEXT:    dcbtst 0, 3, 16
 ; CHECK-AIX64-NEXT:    blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
@@ -55,14 +55,14 @@
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:    lwz 3, 0(3)
-; CHECK-AIX-NEXT:    dcbtt 0, 3
+; CHECK-AIX-NEXT:    dcbt 0, 3, 16
 ; CHECK-AIX-NEXT:    blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtt:
 ; CHECK-AIX64:       # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:    ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:    ld 3, 0(3)
-; CHECK-AIX64-NEXT:    dcbtt 0, 3
+; CHECK-AIX64-NEXT:    dcbt 0, 3, 16
 ; CHECK-AIX64-NEXT:    blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
===================================================================
--- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -158,7 +158,10 @@
   //    dcbt ra, rb, th [server]
   //    dcbt th, ra, rb [embedded]
   //  where th can be omitted when it is 0. dcbtst is the same.
-  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
+  // TODO: AIX still requires dcbtt and dcbtstt implementation,
+  // remove AIX OS check when dcbtt and dcbtstt become available.
+  if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
+      !TT.isOSAIX()) {
     unsigned char TH = MI->getOperand(0).getImm();
     O << "\tdcbt";
     if (MI->getOpcode() == PPC::DCBTST)


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