[PATCH] D111135: [AArch64][SVE] Improve VECTOR_SPLICE codegen for VL > 128-bit

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm accepted this revision.
peterwaller-arm added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll:216
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ext z0.b, z0.b, z1.b, #0
+; CHECK-NEXT:    ext z0.b, z0.b, z1.b, #8
 ; CHECK-NEXT:    ret
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peterwaller-arm wrote:
> I expected to find a #2 here (1 x f16's worth of bytes), but there is a #8, which I can't quickly explain?
A colleague reminded me that this is an unpacked type, so the container fits in 8 bytes. Now it all makes sense.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111135/new/

https://reviews.llvm.org/D111135