[llvm] 94bdc0c - [AArch64] Regenerate some fast-isel tests
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 6 01:30:52 PDT 2021
Author: David Green
Date: 2021-10-06T09:30:48+01:00
New Revision: 94bdc0cf61d5b2b807c1fda96c5fb8d5cc301cea
URL: https://github.com/llvm/llvm-project/commit/94bdc0cf61d5b2b807c1fda96c5fb8d5cc301cea
DIFF: https://github.com/llvm/llvm-project/commit/94bdc0cf61d5b2b807c1fda96c5fb8d5cc301cea.diff
LOG: [AArch64] Regenerate some fast-isel tests
This updates the check lines in some fast isel test, to make them more
maintainable going forward.
Added:
Modified:
llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
llvm/test/CodeGen/AArch64/fast-isel-gep.ll
llvm/test/CodeGen/AArch64/fast-isel-memcpy.ll
llvm/test/CodeGen/AArch64/fast-isel-shift.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll b/llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
index 7aafada46647..076f2a4bd675 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
@@ -1,117 +1,183 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
; Load / Store Base Register only
define zeroext i1 @load_breg_i1(i1* %a) {
-; CHECK-LABEL: load_breg_i1
-; CHECK: ldrb {{w[0-9]+}}, [x0]
+; SDAG-LABEL: load_breg_i1:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: ldrb w0, [x0]
+; SDAG-NEXT: ret
+;
+; FAST-LABEL: load_breg_i1:
+; FAST: ; %bb.0:
+; FAST-NEXT: ldrb w8, [x0]
+; FAST-NEXT: and w8, w8, #0x1
+; FAST-NEXT: and w0, w8, #0x1
+; FAST-NEXT: ret
%1 = load i1, i1* %a
ret i1 %1
}
define zeroext i8 @load_breg_i8(i8* %a) {
-; CHECK-LABEL: load_breg_i8
-; CHECK: ldrb {{w[0-9]+}}, [x0]
+; SDAG-LABEL: load_breg_i8:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: ldrb w0, [x0]
+; SDAG-NEXT: ret
+;
+; FAST-LABEL: load_breg_i8:
+; FAST: ; %bb.0:
+; FAST-NEXT: ldrb w8, [x0]
+; FAST-NEXT: uxtb w0, w8
+; FAST-NEXT: ret
%1 = load i8, i8* %a
ret i8 %1
}
define zeroext i16 @load_breg_i16(i16* %a) {
-; CHECK-LABEL: load_breg_i16
-; CHECK: ldrh {{w[0-9]+}}, [x0]
+; SDAG-LABEL: load_breg_i16:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: ldrh w0, [x0]
+; SDAG-NEXT: ret
+;
+; FAST-LABEL: load_breg_i16:
+; FAST: ; %bb.0:
+; FAST-NEXT: ldrh w8, [x0]
+; FAST-NEXT: uxth w0, w8
+; FAST-NEXT: ret
%1 = load i16, i16* %a
ret i16 %1
}
define i32 @load_breg_i32(i32* %a) {
-; CHECK-LABEL: load_breg_i32
-; CHECK: ldr {{w[0-9]+}}, [x0]
+; CHECK-LABEL: load_breg_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr w0, [x0]
+; CHECK-NEXT: ret
%1 = load i32, i32* %a
ret i32 %1
}
define i64 @load_breg_i64(i64* %a) {
-; CHECK-LABEL: load_breg_i64
-; CHECK: ldr {{x[0-9]+}}, [x0]
+; CHECK-LABEL: load_breg_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr x0, [x0]
+; CHECK-NEXT: ret
%1 = load i64, i64* %a
ret i64 %1
}
define float @load_breg_f32(float* %a) {
-; CHECK-LABEL: load_breg_f32
-; CHECK: ldr {{s[0-9]+}}, [x0]
+; CHECK-LABEL: load_breg_f32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr s0, [x0]
+; CHECK-NEXT: ret
%1 = load float, float* %a
ret float %1
}
define double @load_breg_f64(double* %a) {
-; CHECK-LABEL: load_breg_f64
-; CHECK: ldr {{d[0-9]+}}, [x0]
+; CHECK-LABEL: load_breg_f64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr d0, [x0]
+; CHECK-NEXT: ret
%1 = load double, double* %a
ret double %1
}
define void @store_breg_i1(i1* %a) {
-; CHECK-LABEL: store_breg_i1
-; CHECK: strb wzr, [x0]
+; CHECK-LABEL: store_breg_i1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: strb wzr, [x0]
+; CHECK-NEXT: ret
store i1 0, i1* %a
ret void
}
define void @store_breg_i1_2(i1* %a) {
-; CHECK-LABEL: store_breg_i1_2
-; CHECK: strb {{w[0-9]+}}, [x0]
+; SDAG-LABEL: store_breg_i1_2:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: mov w8, #1
+; SDAG-NEXT: strb w8, [x0]
+; SDAG-NEXT: ret
+;
+; FAST-LABEL: store_breg_i1_2:
+; FAST: ; %bb.0:
+; FAST-NEXT: mov w8, #1
+; FAST-NEXT: and w8, w8, #0x1
+; FAST-NEXT: strb w8, [x0]
+; FAST-NEXT: ret
store i1 true, i1* %a
ret void
}
define void @store_breg_i8(i8* %a) {
-; CHECK-LABEL: store_breg_i8
-; CHECK: strb wzr, [x0]
+; CHECK-LABEL: store_breg_i8:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: strb wzr, [x0]
+; CHECK-NEXT: ret
store i8 0, i8* %a
ret void
}
define void @store_breg_i16(i16* %a) {
-; CHECK-LABEL: store_breg_i16
-; CHECK: strh wzr, [x0]
+; CHECK-LABEL: store_breg_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: strh wzr, [x0]
+; CHECK-NEXT: ret
store i16 0, i16* %a
ret void
}
define void @store_breg_i32(i32* %a) {
-; CHECK-LABEL: store_breg_i32
-; CHECK: str wzr, [x0]
+; CHECK-LABEL: store_breg_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: str wzr, [x0]
+; CHECK-NEXT: ret
store i32 0, i32* %a
ret void
}
define void @store_breg_i64(i64* %a) {
-; CHECK-LABEL: store_breg_i64
-; CHECK: str xzr, [x0]
+; CHECK-LABEL: store_breg_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: str xzr, [x0]
+; CHECK-NEXT: ret
store i64 0, i64* %a
ret void
}
define void @store_breg_f32(float* %a) {
-; CHECK-LABEL: store_breg_f32
-; CHECK: str wzr, [x0]
+; CHECK-LABEL: store_breg_f32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: str wzr, [x0]
+; CHECK-NEXT: ret
store float 0.0, float* %a
ret void
}
define void @store_breg_f64(double* %a) {
-; CHECK-LABEL: store_breg_f64
-; CHECK: str xzr, [x0]
+; CHECK-LABEL: store_breg_f64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: str xzr, [x0]
+; CHECK-NEXT: ret
store double 0.0, double* %a
ret void
}
; Load Immediate
define i32 @load_immoff_1() {
-; CHECK-LABEL: load_immoff_1
-; CHECK: mov {{w|x}}[[REG:[0-9]+]], #128
-; CHECK: ldr {{w[0-9]+}}, {{\[}}x[[REG]]{{\]}}
+; SDAG-LABEL: load_immoff_1:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: mov w8, #128
+; SDAG-NEXT: ldr w0, [x8]
+; SDAG-NEXT: ret
+;
+; FAST-LABEL: load_immoff_1:
+; FAST: ; %bb.0:
+; FAST-NEXT: mov x8, #128
+; FAST-NEXT: ldr w0, [x8]
+; FAST-NEXT: ret
%1 = inttoptr i64 128 to i32*
%2 = load i32, i32* %1
ret i32 %2
@@ -120,8 +186,10 @@ define i32 @load_immoff_1() {
; Load / Store Base Register + Immediate Offset
; Max supported negative offset
define i32 @load_breg_immoff_1(i64 %a) {
-; CHECK-LABEL: load_breg_immoff_1
-; CHECK: ldur {{w[0-9]+}}, [x0, #-256]
+; CHECK-LABEL: load_breg_immoff_1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldur w0, [x0, #-256]
+; CHECK-NEXT: ret
%1 = add i64 %a, -256
%2 = inttoptr i64 %1 to i32*
%3 = load i32, i32* %2
@@ -130,9 +198,11 @@ define i32 @load_breg_immoff_1(i64 %a) {
; Min not-supported negative offset
define i32 @load_breg_immoff_2(i64 %a) {
-; CHECK-LABEL: load_breg_immoff_2
-; CHECK: sub [[REG:x[0-9]+]], x0, #257
-; CHECK-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
+; CHECK-LABEL: load_breg_immoff_2:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sub x8, x0, #257
+; CHECK-NEXT: ldr w0, [x8]
+; CHECK-NEXT: ret
%1 = add i64 %a, -257
%2 = inttoptr i64 %1 to i32*
%3 = load i32, i32* %2
@@ -141,8 +211,10 @@ define i32 @load_breg_immoff_2(i64 %a) {
; Max supported unscaled offset
define i32 @load_breg_immoff_3(i64 %a) {
-; CHECK-LABEL: load_breg_immoff_3
-; CHECK: ldur {{w[0-9]+}}, [x0, #255]
+; CHECK-LABEL: load_breg_immoff_3:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldur w0, [x0, #255]
+; CHECK-NEXT: ret
%1 = add i64 %a, 255
%2 = inttoptr i64 %1 to i32*
%3 = load i32, i32* %2
@@ -151,9 +223,11 @@ define i32 @load_breg_immoff_3(i64 %a) {
; Min un-supported unscaled offset
define i32 @load_breg_immoff_4(i64 %a) {
-; CHECK-LABEL: load_breg_immoff_4
-; CHECK: add [[REG:x[0-9]+]], x0, #257
-; CHECK-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
+; CHECK-LABEL: load_breg_immoff_4:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: add x8, x0, #257
+; CHECK-NEXT: ldr w0, [x8]
+; CHECK-NEXT: ret
%1 = add i64 %a, 257
%2 = inttoptr i64 %1 to i32*
%3 = load i32, i32* %2
@@ -162,8 +236,10 @@ define i32 @load_breg_immoff_4(i64 %a) {
; Max supported scaled offset
define i32 @load_breg_immoff_5(i64 %a) {
-; CHECK-LABEL: load_breg_immoff_5
-; CHECK: ldr {{w[0-9]+}}, [x0, #16380]
+; CHECK-LABEL: load_breg_immoff_5:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr w0, [x0, #16380]
+; CHECK-NEXT: ret
%1 = add i64 %a, 16380
%2 = inttoptr i64 %1 to i32*
%3 = load i32, i32* %2
@@ -172,12 +248,17 @@ define i32 @load_breg_immoff_5(i64 %a) {
; Min un-supported scaled offset
define i32 @load_breg_immoff_6(i64 %a) {
-; SDAG-LABEL: load_breg_immoff_6
-; SDAG: mov w[[NUM:[0-9]+]], #16384
-; SDAG-NEXT: ldr {{w[0-9]+}}, [x0, x[[NUM]]]
-; FAST-LABEL: load_breg_immoff_6
-; FAST: add [[REG:x[0-9]+]], x0, #4, lsl #12
-; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
+; SDAG-LABEL: load_breg_immoff_6:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: mov w8, #16384
+; SDAG-NEXT: ldr w0, [x0, x8]
+; SDAG-NEXT: ret
+;
+; FAST-LABEL: load_breg_immoff_6:
+; FAST: ; %bb.0:
+; FAST-NEXT: add x8, x0, #4, lsl #12 ; =16384
+; FAST-NEXT: ldr w0, [x8]
+; FAST-NEXT: ret
%1 = add i64 %a, 16384
%2 = inttoptr i64 %1 to i32*
%3 = load i32, i32* %2
@@ -186,8 +267,10 @@ define i32 @load_breg_immoff_6(i64 %a) {
; Max supported negative offset
define void @store_breg_immoff_1(i64 %a) {
-; CHECK-LABEL: store_breg_immoff_1
-; CHECK: stur wzr, [x0, #-256]
+; CHECK-LABEL: store_breg_immoff_1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: stur wzr, [x0, #-256]
+; CHECK-NEXT: ret
%1 = add i64 %a, -256
%2 = inttoptr i64 %1 to i32*
store i32 0, i32* %2
@@ -196,9 +279,11 @@ define void @store_breg_immoff_1(i64 %a) {
; Min not-supported negative offset
define void @store_breg_immoff_2(i64 %a) {
-; CHECK-LABEL: store_breg_immoff_2
-; CHECK: sub [[REG:x[0-9]+]], x0, #257
-; CHECK-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
+; CHECK-LABEL: store_breg_immoff_2:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sub x8, x0, #257
+; CHECK-NEXT: str wzr, [x8]
+; CHECK-NEXT: ret
%1 = add i64 %a, -257
%2 = inttoptr i64 %1 to i32*
store i32 0, i32* %2
@@ -207,8 +292,10 @@ define void @store_breg_immoff_2(i64 %a) {
; Max supported unscaled offset
define void @store_breg_immoff_3(i64 %a) {
-; CHECK-LABEL: store_breg_immoff_3
-; CHECK: stur wzr, [x0, #255]
+; CHECK-LABEL: store_breg_immoff_3:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: stur wzr, [x0, #255]
+; CHECK-NEXT: ret
%1 = add i64 %a, 255
%2 = inttoptr i64 %1 to i32*
store i32 0, i32* %2
@@ -217,9 +304,11 @@ define void @store_breg_immoff_3(i64 %a) {
; Min un-supported unscaled offset
define void @store_breg_immoff_4(i64 %a) {
-; CHECK-LABEL: store_breg_immoff_4
-; CHECK: add [[REG:x[0-9]+]], x0, #257
-; CHECK-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
+; CHECK-LABEL: store_breg_immoff_4:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: add x8, x0, #257
+; CHECK-NEXT: str wzr, [x8]
+; CHECK-NEXT: ret
%1 = add i64 %a, 257
%2 = inttoptr i64 %1 to i32*
store i32 0, i32* %2
@@ -228,8 +317,10 @@ define void @store_breg_immoff_4(i64 %a) {
; Max supported scaled offset
define void @store_breg_immoff_5(i64 %a) {
-; CHECK-LABEL: store_breg_immoff_5
-; CHECK: str wzr, [x0, #16380]
+; CHECK-LABEL: store_breg_immoff_5:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: str wzr, [x0, #16380]
+; CHECK-NEXT: ret
%1 = add i64 %a, 16380
%2 = inttoptr i64 %1 to i32*
store i32 0, i32* %2
@@ -238,12 +329,17 @@ define void @store_breg_immoff_5(i64 %a) {
; Min un-supported scaled offset
define void @store_breg_immoff_6(i64 %a) {
-; SDAG-LABEL: store_breg_immoff_6
-; SDAG: mov w[[NUM:[0-9]+]], #16384
-; SDAG-NEXT: str wzr, [x0, x[[NUM]]]
-; FAST-LABEL: store_breg_immoff_6
-; FAST: add [[REG:x[0-9]+]], x0, #4, lsl #12
-; FAST-NEXT: str wzr, {{\[}}[[REG]]{{\]}}
+; SDAG-LABEL: store_breg_immoff_6:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: mov w8, #16384
+; SDAG-NEXT: str wzr, [x0, x8]
+; SDAG-NEXT: ret
+;
+; FAST-LABEL: store_breg_immoff_6:
+; FAST: ; %bb.0:
+; FAST-NEXT: add x8, x0, #4, lsl #12 ; =16384
+; FAST-NEXT: str wzr, [x8]
+; FAST-NEXT: ret
%1 = add i64 %a, 16384
%2 = inttoptr i64 %1 to i32*
store i32 0, i32* %2
@@ -251,8 +347,10 @@ define void @store_breg_immoff_6(i64 %a) {
}
define i64 @load_breg_immoff_7(i64 %a) {
-; CHECK-LABEL: load_breg_immoff_7
-; CHECK: ldr {{x[0-9]+}}, [x0, #48]
+; CHECK-LABEL: load_breg_immoff_7:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr x0, [x0, #48]
+; CHECK-NEXT: ret
%1 = add i64 %a, 48
%2 = inttoptr i64 %1 to i64*
%3 = load i64, i64* %2
@@ -261,8 +359,10 @@ define i64 @load_breg_immoff_7(i64 %a) {
; Flip add operands
define i64 @load_breg_immoff_8(i64 %a) {
-; CHECK-LABEL: load_breg_immoff_8
-; CHECK: ldr {{x[0-9]+}}, [x0, #48]
+; CHECK-LABEL: load_breg_immoff_8:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr x0, [x0, #48]
+; CHECK-NEXT: ret
%1 = add i64 48, %a
%2 = inttoptr i64 %1 to i64*
%3 = load i64, i64* %2
@@ -271,8 +371,10 @@ define i64 @load_breg_immoff_8(i64 %a) {
; Load Base Register + Register Offset
define i64 @load_breg_offreg_1(i64 %a, i64 %b) {
-; CHECK-LABEL: load_breg_offreg_1
-; CHECK: ldr {{x[0-9]+}}, [x0, x1]
+; CHECK-LABEL: load_breg_offreg_1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr x0, [x0, x1]
+; CHECK-NEXT: ret
%1 = add i64 %a, %b
%2 = inttoptr i64 %1 to i64*
%3 = load i64, i64* %2
@@ -281,8 +383,10 @@ define i64 @load_breg_offreg_1(i64 %a, i64 %b) {
; Flip add operands
define i64 @load_breg_offreg_2(i64 %a, i64 %b) {
-; CHECK-LABEL: load_breg_offreg_2
-; CHECK: ldr {{x[0-9]+}}, [x1, x0]
+; CHECK-LABEL: load_breg_offreg_2:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr x0, [x1, x0]
+; CHECK-NEXT: ret
%1 = add i64 %b, %a
%2 = inttoptr i64 %1 to i64*
%3 = load i64, i64* %2
@@ -291,9 +395,11 @@ define i64 @load_breg_offreg_2(i64 %a, i64 %b) {
; Load Base Register + Register Offset + Immediate Offset
define i64 @load_breg_offreg_immoff_1(i64 %a, i64 %b) {
-; CHECK-LABEL: load_breg_offreg_immoff_1
-; CHECK: add [[REG:x[0-9]+]], x0, x1
-; CHECK-NEXT: ldr x0, {{\[}}[[REG]], #48{{\]}}
+; CHECK-LABEL: load_breg_offreg_immoff_1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: add x8, x0, x1
+; CHECK-NEXT: ldr x0, [x8, #48]
+; CHECK-NEXT: ret
%1 = add i64 %a, %b
%2 = add i64 %1, 48
%3 = inttoptr i64 %2 to i64*
@@ -302,13 +408,18 @@ define i64 @load_breg_offreg_immoff_1(i64 %a, i64 %b) {
}
define i64 @load_breg_offreg_immoff_2(i64 %a, i64 %b) {
-; SDAG-LABEL: load_breg_offreg_immoff_2
-; SDAG: add [[REG1:x[0-9]+]], x0, x1
-; SDAG-NEXT: mov w[[NUM:[0-9]+]], #61440
-; SDAG-NEXT: ldr x0, {{\[}}[[REG1]], x[[NUM]]]
-; FAST-LABEL: load_breg_offreg_immoff_2
-; FAST: add [[REG:x[0-9]+]], x0, #15, lsl #12
-; FAST-NEXT: ldr x0, {{\[}}[[REG]], x1{{\]}}
+; SDAG-LABEL: load_breg_offreg_immoff_2:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: add x8, x0, x1
+; SDAG-NEXT: mov w9, #61440
+; SDAG-NEXT: ldr x0, [x8, x9]
+; SDAG-NEXT: ret
+;
+; FAST-LABEL: load_breg_offreg_immoff_2:
+; FAST: ; %bb.0:
+; FAST-NEXT: add x8, x0, #15, lsl #12 ; =61440
+; FAST-NEXT: ldr x0, [x8, x1]
+; FAST-NEXT: ret
%1 = add i64 %a, %b
%2 = add i64 %1, 61440
%3 = inttoptr i64 %2 to i64*
@@ -318,9 +429,11 @@ define i64 @load_breg_offreg_immoff_2(i64 %a, i64 %b) {
; Load Scaled Register Offset
define i32 @load_shift_offreg_1(i64 %a) {
-; CHECK-LABEL: load_shift_offreg_1
-; CHECK: lsl [[REG:x[0-9]+]], x0, #2
-; CHECK: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
+; CHECK-LABEL: load_shift_offreg_1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: lsl x8, x0, #2
+; CHECK-NEXT: ldr w0, [x8]
+; CHECK-NEXT: ret
%1 = shl i64 %a, 2
%2 = inttoptr i64 %1 to i32*
%3 = load i32, i32* %2
@@ -328,9 +441,11 @@ define i32 @load_shift_offreg_1(i64 %a) {
}
define i32 @load_mul_offreg_1(i64 %a) {
-; CHECK-LABEL: load_mul_offreg_1
-; CHECK: lsl [[REG:x[0-9]+]], x0, #2
-; CHECK: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}}
+; CHECK-LABEL: load_mul_offreg_1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: lsl x8, x0, #2
+; CHECK-NEXT: ldr w0, [x8]
+; CHECK-NEXT: ret
%1 = mul i64 %a, 4
%2 = inttoptr i64 %1 to i32*
%3 = load i32, i32* %2
@@ -339,8 +454,10 @@ define i32 @load_mul_offreg_1(i64 %a) {
; Load Base Register + Scaled Register Offset
define i32 @load_breg_shift_offreg_1(i64 %a, i64 %b) {
-; CHECK-LABEL: load_breg_shift_offreg_1
-; CHECK: ldr {{w[0-9]+}}, [x1, x0, lsl #2]
+; CHECK-LABEL: load_breg_shift_offreg_1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr w0, [x1, x0, lsl #2]
+; CHECK-NEXT: ret
%1 = shl i64 %a, 2
%2 = add i64 %1, %b
%3 = inttoptr i64 %2 to i32*
@@ -349,8 +466,10 @@ define i32 @load_breg_shift_offreg_1(i64 %a, i64 %b) {
}
define i32 @load_breg_shift_offreg_2(i64 %a, i64 %b) {
-; CHECK-LABEL: load_breg_shift_offreg_2
-; CHECK: ldr {{w[0-9]+}}, [x1, x0, lsl #2]
+; CHECK-LABEL: load_breg_shift_offreg_2:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr w0, [x1, x0, lsl #2]
+; CHECK-NEXT: ret
%1 = shl i64 %a, 2
%2 = add i64 %b, %1
%3 = inttoptr i64 %2 to i32*
@@ -359,12 +478,17 @@ define i32 @load_breg_shift_offreg_2(i64 %a, i64 %b) {
}
define i32 @load_breg_shift_offreg_3(i64 %a, i64 %b) {
-; SDAG-LABEL: load_breg_shift_offreg_3
-; SDAG: lsl [[REG:x[0-9]+]], x0, #2
-; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x1, lsl #2{{\]}}
-; FAST-LABEL: load_breg_shift_offreg_3
-; FAST: lsl [[REG:x[0-9]+]], x1, #2
-; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
+; SDAG-LABEL: load_breg_shift_offreg_3:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: lsl x8, x0, #2
+; SDAG-NEXT: ldr w0, [x8, x1, lsl #2]
+; SDAG-NEXT: ret
+;
+; FAST-LABEL: load_breg_shift_offreg_3:
+; FAST: ; %bb.0:
+; FAST-NEXT: lsl x8, x1, #2
+; FAST-NEXT: ldr w0, [x8, x0, lsl #2]
+; FAST-NEXT: ret
%1 = shl i64 %a, 2
%2 = shl i64 %b, 2
%3 = add i64 %1, %2
@@ -374,12 +498,17 @@ define i32 @load_breg_shift_offreg_3(i64 %a, i64 %b) {
}
define i32 @load_breg_shift_offreg_4(i64 %a, i64 %b) {
-; SDAG-LABEL: load_breg_shift_offreg_4
-; SDAG: lsl [[REG:x[0-9]+]], x1, #2
-; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
-; FAST-LABEL: load_breg_shift_offreg_4
-; FAST: lsl [[REG:x[0-9]+]], x0, #2
-; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x1, lsl #2{{\]}}
+; SDAG-LABEL: load_breg_shift_offreg_4:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: lsl x8, x1, #2
+; SDAG-NEXT: ldr w0, [x8, x0, lsl #2]
+; SDAG-NEXT: ret
+;
+; FAST-LABEL: load_breg_shift_offreg_4:
+; FAST: ; %bb.0:
+; FAST-NEXT: lsl x8, x0, #2
+; FAST-NEXT: ldr w0, [x8, x1, lsl #2]
+; FAST-NEXT: ret
%1 = shl i64 %a, 2
%2 = shl i64 %b, 2
%3 = add i64 %2, %1
@@ -389,12 +518,11 @@ define i32 @load_breg_shift_offreg_4(i64 %a, i64 %b) {
}
define i32 @load_breg_shift_offreg_5(i64 %a, i64 %b) {
-; SDAG-LABEL: load_breg_shift_offreg_5
-; SDAG: lsl [[REG:x[0-9]+]], x1, #3
-; SDAG-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
-; FAST-LABEL: load_breg_shift_offreg_5
-; FAST: lsl [[REG:x[0-9]+]], x1, #3
-; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
+; CHECK-LABEL: load_breg_shift_offreg_5:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: lsl x8, x1, #3
+; CHECK-NEXT: ldr w0, [x8, x0, lsl #2]
+; CHECK-NEXT: ret
%1 = shl i64 %a, 2
%2 = shl i64 %b, 3
%3 = add i64 %1, %2
@@ -404,8 +532,10 @@ define i32 @load_breg_shift_offreg_5(i64 %a, i64 %b) {
}
define i32 @load_breg_mul_offreg_1(i64 %a, i64 %b) {
-; CHECK-LABEL: load_breg_mul_offreg_1
-; CHECK: ldr {{w[0-9]+}}, [x1, x0, lsl #2]
+; CHECK-LABEL: load_breg_mul_offreg_1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr w0, [x1, x0, lsl #2]
+; CHECK-NEXT: ret
%1 = mul i64 %a, 4
%2 = add i64 %1, %b
%3 = inttoptr i64 %2 to i32*
@@ -414,8 +544,16 @@ define i32 @load_breg_mul_offreg_1(i64 %a, i64 %b) {
}
define zeroext i8 @load_breg_and_offreg_1(i64 %a, i64 %b) {
-; CHECK-LABEL: load_breg_and_offreg_1
-; CHECK: ldrb {{w[0-9]+}}, [x1, w0, uxtw]
+; SDAG-LABEL: load_breg_and_offreg_1:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: ldrb w0, [x1, w0, uxtw]
+; SDAG-NEXT: ret
+;
+; FAST-LABEL: load_breg_and_offreg_1:
+; FAST: ; %bb.0:
+; FAST-NEXT: ldrb w8, [x1, w0, uxtw]
+; FAST-NEXT: uxtb w0, w8
+; FAST-NEXT: ret
%1 = and i64 %a, 4294967295
%2 = add i64 %1, %b
%3 = inttoptr i64 %2 to i8*
@@ -424,8 +562,16 @@ define zeroext i8 @load_breg_and_offreg_1(i64 %a, i64 %b) {
}
define zeroext i16 @load_breg_and_offreg_2(i64 %a, i64 %b) {
-; CHECK-LABEL: load_breg_and_offreg_2
-; CHECK: ldrh {{w[0-9]+}}, [x1, w0, uxtw #1]
+; SDAG-LABEL: load_breg_and_offreg_2:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: ldrh w0, [x1, w0, uxtw #1]
+; SDAG-NEXT: ret
+;
+; FAST-LABEL: load_breg_and_offreg_2:
+; FAST: ; %bb.0:
+; FAST-NEXT: ldrh w8, [x1, w0, uxtw #1]
+; FAST-NEXT: uxth w0, w8
+; FAST-NEXT: ret
%1 = and i64 %a, 4294967295
%2 = shl i64 %1, 1
%3 = add i64 %2, %b
@@ -435,8 +581,10 @@ define zeroext i16 @load_breg_and_offreg_2(i64 %a, i64 %b) {
}
define i32 @load_breg_and_offreg_3(i64 %a, i64 %b) {
-; CHECK-LABEL: load_breg_and_offreg_3
-; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2]
+; CHECK-LABEL: load_breg_and_offreg_3:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr w0, [x1, w0, uxtw #2]
+; CHECK-NEXT: ret
%1 = and i64 %a, 4294967295
%2 = shl i64 %1, 2
%3 = add i64 %2, %b
@@ -446,8 +594,10 @@ define i32 @load_breg_and_offreg_3(i64 %a, i64 %b) {
}
define i64 @load_breg_and_offreg_4(i64 %a, i64 %b) {
-; CHECK-LABEL: load_breg_and_offreg_4
-; CHECK: ldr {{x[0-9]+}}, [x1, w0, uxtw #3]
+; CHECK-LABEL: load_breg_and_offreg_4:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr x0, [x1, w0, uxtw #3]
+; CHECK-NEXT: ret
%1 = and i64 %a, 4294967295
%2 = shl i64 %1, 3
%3 = add i64 %2, %b
@@ -458,9 +608,11 @@ define i64 @load_breg_and_offreg_4(i64 %a, i64 %b) {
; Not all 'and' instructions have immediates.
define i64 @load_breg_and_offreg_5(i64 %a, i64 %b, i64 %c) {
-; CHECK-LABEL: load_breg_and_offreg_5
-; CHECK: and [[REG:x[0-9]+]], x0, x2
-; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}[[REG]], x1{{\]}}
+; CHECK-LABEL: load_breg_and_offreg_5:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: and x8, x0, x2
+; CHECK-NEXT: ldr x0, [x8, x1]
+; CHECK-NEXT: ret
%1 = and i64 %a, %c
%2 = add i64 %1, %b
%3 = inttoptr i64 %2 to i64*
@@ -469,9 +621,11 @@ define i64 @load_breg_and_offreg_5(i64 %a, i64 %b, i64 %c) {
}
define i64 @load_breg_and_offreg_6(i64 %a, i64 %b, i64 %c) {
-; CHECK-LABEL: load_breg_and_offreg_6
-; CHECK: and [[REG:x[0-9]+]], x0, x2
-; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}x1, [[REG]], lsl #3{{\]}}
+; CHECK-LABEL: load_breg_and_offreg_6:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: and x8, x0, x2
+; CHECK-NEXT: ldr x0, [x1, x8, lsl #3]
+; CHECK-NEXT: ret
%1 = and i64 %a, %c
%2 = shl i64 %1, 3
%3 = add i64 %2, %b
@@ -482,8 +636,10 @@ define i64 @load_breg_and_offreg_6(i64 %a, i64 %b, i64 %c) {
; Load Base Register + Scaled Register Offset + Sign/Zero extension
define i32 @load_breg_zext_shift_offreg_1(i32 %a, i64 %b) {
-; CHECK-LABEL: load_breg_zext_shift_offreg_1
-; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2]
+; CHECK-LABEL: load_breg_zext_shift_offreg_1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr w0, [x1, w0, uxtw #2]
+; CHECK-NEXT: ret
%1 = zext i32 %a to i64
%2 = shl i64 %1, 2
%3 = add i64 %2, %b
@@ -493,8 +649,10 @@ define i32 @load_breg_zext_shift_offreg_1(i32 %a, i64 %b) {
}
define i32 @load_breg_zext_shift_offreg_2(i32 %a, i64 %b) {
-; CHECK-LABEL: load_breg_zext_shift_offreg_2
-; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2]
+; CHECK-LABEL: load_breg_zext_shift_offreg_2:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr w0, [x1, w0, uxtw #2]
+; CHECK-NEXT: ret
%1 = zext i32 %a to i64
%2 = shl i64 %1, 2
%3 = add i64 %b, %2
@@ -504,8 +662,10 @@ define i32 @load_breg_zext_shift_offreg_2(i32 %a, i64 %b) {
}
define i32 @load_breg_zext_mul_offreg_1(i32 %a, i64 %b) {
-; CHECK-LABEL: load_breg_zext_mul_offreg_1
-; CHECK: ldr {{w[0-9]+}}, [x1, w0, uxtw #2]
+; CHECK-LABEL: load_breg_zext_mul_offreg_1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr w0, [x1, w0, uxtw #2]
+; CHECK-NEXT: ret
%1 = zext i32 %a to i64
%2 = mul i64 %1, 4
%3 = add i64 %2, %b
@@ -515,8 +675,10 @@ define i32 @load_breg_zext_mul_offreg_1(i32 %a, i64 %b) {
}
define i32 @load_breg_sext_shift_offreg_1(i32 %a, i64 %b) {
-; CHECK-LABEL: load_breg_sext_shift_offreg_1
-; CHECK: ldr {{w[0-9]+}}, [x1, w0, sxtw #2]
+; CHECK-LABEL: load_breg_sext_shift_offreg_1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr w0, [x1, w0, sxtw #2]
+; CHECK-NEXT: ret
%1 = sext i32 %a to i64
%2 = shl i64 %1, 2
%3 = add i64 %2, %b
@@ -526,8 +688,10 @@ define i32 @load_breg_sext_shift_offreg_1(i32 %a, i64 %b) {
}
define i32 @load_breg_sext_shift_offreg_2(i32 %a, i64 %b) {
-; CHECK-LABEL: load_breg_sext_shift_offreg_2
-; CHECK: ldr {{w[0-9]+}}, [x1, w0, sxtw #2]
+; CHECK-LABEL: load_breg_sext_shift_offreg_2:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr w0, [x1, w0, sxtw #2]
+; CHECK-NEXT: ret
%1 = sext i32 %a to i64
%2 = shl i64 %1, 2
%3 = add i64 %b, %2
@@ -538,9 +702,11 @@ define i32 @load_breg_sext_shift_offreg_2(i32 %a, i64 %b) {
; Make sure that we don't drop the first 'add' instruction.
define i32 @load_breg_sext_shift_offreg_3(i32 %a, i64 %b) {
-; CHECK-LABEL: load_breg_sext_shift_offreg_3
-; CHECK: add [[REG:w[0-9]+]], w0, #4
-; CHECK: ldr {{w[0-9]+}}, {{\[}}x1, [[REG]], sxtw #2{{\]}}
+; CHECK-LABEL: load_breg_sext_shift_offreg_3:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: add w8, w0, #4
+; CHECK-NEXT: ldr w0, [x1, w8, sxtw #2]
+; CHECK-NEXT: ret
%1 = add i32 %a, 4
%2 = sext i32 %1 to i64
%3 = shl i64 %2, 2
@@ -552,8 +718,10 @@ define i32 @load_breg_sext_shift_offreg_3(i32 %a, i64 %b) {
define i32 @load_breg_sext_mul_offreg_1(i32 %a, i64 %b) {
-; CHECK-LABEL: load_breg_sext_mul_offreg_1
-; CHECK: ldr {{w[0-9]+}}, [x1, w0, sxtw #2]
+; CHECK-LABEL: load_breg_sext_mul_offreg_1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr w0, [x1, w0, sxtw #2]
+; CHECK-NEXT: ret
%1 = sext i32 %a to i64
%2 = mul i64 %1, 4
%3 = add i64 %2, %b
@@ -564,9 +732,12 @@ define i32 @load_breg_sext_mul_offreg_1(i32 %a, i64 %b) {
; Load Scaled Register Offset + Immediate Offset + Sign/Zero extension
define i64 @load_sext_shift_offreg_imm1(i32 %a) {
-; CHECK-LABEL: load_sext_shift_offreg_imm1
-; CHECK: sbfiz [[REG:x[0-9]+]], {{x[0-9]+}}, #3, #32
-; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}[[REG]], #8{{\]}}
+; CHECK-LABEL: load_sext_shift_offreg_imm1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfiz x8, x0, #3, #32
+; CHECK-NEXT: ldr x0, [x8, #8]
+; CHECK-NEXT: ret
%1 = sext i32 %a to i64
%2 = shl i64 %1, 3
%3 = add i64 %2, 8
@@ -577,9 +748,11 @@ define i64 @load_sext_shift_offreg_imm1(i32 %a) {
; Load Base Register + Scaled Register Offset + Immediate Offset + Sign/Zero extension
define i64 @load_breg_sext_shift_offreg_imm1(i32 %a, i64 %b) {
-; CHECK-LABEL: load_breg_sext_shift_offreg_imm1
-; CHECK: add [[REG:x[0-9]+]], x1, w0, sxtw #3
-; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}[[REG]], #8{{\]}}
+; CHECK-LABEL: load_breg_sext_shift_offreg_imm1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: add x8, x1, w0, sxtw #3
+; CHECK-NEXT: ldr x0, [x8, #8]
+; CHECK-NEXT: ret
%1 = sext i32 %a to i64
%2 = shl i64 %1, 3
%3 = add i64 %b, %2
@@ -591,6 +764,19 @@ define i64 @load_breg_sext_shift_offreg_imm1(i32 %a, i64 %b) {
; Test that the kill flag is not set - the machine instruction verifier does that for us.
define i64 @kill_reg(i64 %a) {
+; SDAG-LABEL: kill_reg:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: ldr x8, [x0, #88]!
+; SDAG-NEXT: add x0, x0, x8
+; SDAG-NEXT: ret
+;
+; FAST-LABEL: kill_reg:
+; FAST: ; %bb.0:
+; FAST-NEXT: ldr x8, [x0, #88]
+; FAST-NEXT: sub x9, x0, #8
+; FAST-NEXT: add x9, x9, #96
+; FAST-NEXT: add x0, x9, x8
+; FAST-NEXT: ret
%1 = sub i64 %a, 8
%2 = add i64 %1, 96
%3 = inttoptr i64 %2 to i64*
@@ -600,9 +786,25 @@ define i64 @kill_reg(i64 %a) {
}
define void @store_fi(i64 %i) {
-; CHECK-LABEL: store_fi
-; CHECK: mov [[REG:x[0-9]+]], sp
-; CHECK: str {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
+; SDAG-LABEL: store_fi:
+; SDAG: ; %bb.0:
+; SDAG-NEXT: sub sp, sp, #32
+; SDAG-NEXT: .cfi_def_cfa_offset 32
+; SDAG-NEXT: mov x8, sp
+; SDAG-NEXT: mov w9, #47
+; SDAG-NEXT: str w9, [x8, x0, lsl #2]
+; SDAG-NEXT: add sp, sp, #32
+; SDAG-NEXT: ret
+;
+; FAST-LABEL: store_fi:
+; FAST: ; %bb.0:
+; FAST-NEXT: sub sp, sp, #32
+; FAST-NEXT: .cfi_def_cfa_offset 32
+; FAST-NEXT: mov w8, #47
+; FAST-NEXT: mov x9, sp
+; FAST-NEXT: str w8, [x9, x0, lsl #2]
+; FAST-NEXT: add sp, sp, #32
+; FAST-NEXT: ret
%1 = alloca [8 x i32]
%2 = ptrtoint [8 x i32]* %1 to i64
%3 = mul i64 %i, 4
@@ -613,9 +815,14 @@ define void @store_fi(i64 %i) {
}
define i32 @load_fi(i64 %i) {
-; CHECK-LABEL: load_fi
-; CHECK: mov [[REG:x[0-9]+]], sp
-; CHECK: ldr {{w[0-9]+}}, {{\[}}[[REG]], x0, lsl #2{{\]}}
+; CHECK-LABEL: load_fi:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sub sp, sp, #32
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: mov x8, sp
+; CHECK-NEXT: ldr w0, [x8, x0, lsl #2]
+; CHECK-NEXT: add sp, sp, #32
+; CHECK-NEXT: ret
%1 = alloca [8 x i32]
%2 = ptrtoint [8 x i32]* %1 to i64
%3 = mul i64 %i, 4
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-gep.ll b/llvm/test/CodeGen/AArch64/fast-isel-gep.ll
index 2d38bc44c4ec..e20723e0ff19 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-gep.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-gep.ll
@@ -1,49 +1,63 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
%struct.foo = type { i32, i64, float, double }
define double* @test_struct(%struct.foo* %f) {
-; CHECK-LABEL: test_struct
-; CHECK: add x0, x0, #24
+; CHECK-LABEL: test_struct:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: add x0, x0, #24
+; CHECK-NEXT: ret
%1 = getelementptr inbounds %struct.foo, %struct.foo* %f, i64 0, i32 3
ret double* %1
}
define i32* @test_array1(i32* %a, i64 %i) {
-; CHECK-LABEL: test_array1
-; CHECK: mov [[REG:x[0-9]+]], #4
-; CHECK-NEXT: madd x0, x1, [[REG]], x0
+; CHECK-LABEL: test_array1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov x8, #4
+; CHECK-NEXT: madd x0, x1, x8, x0
+; CHECK-NEXT: ret
%1 = getelementptr inbounds i32, i32* %a, i64 %i
ret i32* %1
}
define i32* @test_array2(i32* %a) {
-; CHECK-LABEL: test_array2
-; CHECK: add x0, x0, #16
+; CHECK-LABEL: test_array2:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: add x0, x0, #16
+; CHECK-NEXT: ret
%1 = getelementptr inbounds i32, i32* %a, i64 4
ret i32* %1
}
define i32* @test_array3(i32* %a) {
-; CHECK-LABEL: test_array3
-; CHECK: add x0, x0, #1, lsl #12
+; CHECK-LABEL: test_array3:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: add x0, x0, #1, lsl #12 ; =4096
+; CHECK-NEXT: ret
%1 = getelementptr inbounds i32, i32* %a, i64 1024
ret i32* %1
}
define i32* @test_array4(i32* %a) {
-; CHECK-LABEL: test_array4
-; CHECK: mov [[REG:x[0-9]+]], #4104
-; CHECK-NEXT: add x0, x0, [[REG]]
+; CHECK-LABEL: test_array4:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov x8, #4104
+; CHECK-NEXT: add x0, x0, x8
+; CHECK-NEXT: ret
%1 = getelementptr inbounds i32, i32* %a, i64 1026
ret i32* %1
}
define i32* @test_array5(i32* %a, i32 %i) {
-; CHECK-LABEL: test_array5
-; CHECK: sxtw [[REG1:x[0-9]+]], w1
-; CHECK-NEXT: mov [[REG2:x[0-9]+]], #4
-; CHECK-NEXT: madd {{x[0-9]+}}, [[REG1]], [[REG2]], x0
+; CHECK-LABEL: test_array5:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT: sxtw x8, w1
+; CHECK-NEXT: mov x9, #4
+; CHECK-NEXT: madd x0, x8, x9, x0
+; CHECK-NEXT: ret
%1 = getelementptr inbounds i32, i32* %a, i32 %i
ret i32* %1
}
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-memcpy.ll b/llvm/test/CodeGen/AArch64/fast-isel-memcpy.ll
index 290e0c918ade..b78016145264 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-memcpy.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-memcpy.ll
@@ -1,11 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
; Test that we don't segfault.
-; CHECK-LABEL: test
-; CHECK: ldr [[REG1:x[0-9]+]], [x1]
-; CHECK-NEXT: and [[REG2:x[0-9]+]], x0, #0x7fffffffffffffff
-; CHECK-NEXT: str [[REG1]], {{\[}}[[REG2]]{{\]}}
define void @test(i64 %a, i8* %b) {
+; CHECK-LABEL: test:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ldr x8, [x1]
+; CHECK-NEXT: and x9, x0, #0x7fffffffffffffff
+; CHECK-NEXT: str x8, [x9]
+; CHECK-NEXT: ret
%1 = and i64 %a, 9223372036854775807
%2 = inttoptr i64 %1 to i8*
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %2, i8* align 8 %b, i64 8, i1 false)
diff --git a/llvm/test/CodeGen/AArch64/fast-isel-shift.ll b/llvm/test/CodeGen/AArch64/fast-isel-shift.ll
index 36fab0d51ed5..95891db80bc4 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-shift.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-shift.ll
@@ -1,495 +1,650 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -fast-isel -fast-isel-abort=1 -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s
-; CHECK-LABEL: asr_zext_i1_i16
-; CHECK: uxth {{w[0-9]*}}, wzr
define zeroext i16 @asr_zext_i1_i16(i1 %b) {
+; CHECK-LABEL: asr_zext_i1_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: uxth w0, wzr
+; CHECK-NEXT: ret
%1 = zext i1 %b to i16
%2 = ashr i16 %1, 1
ret i16 %2
}
-; CHECK-LABEL: asr_sext_i1_i16
-; CHECK: sbfx [[REG1:w[0-9]+]], {{w[0-9]*}}, #0, #1
-; CHECK-NEXT: sxth {{w[0-9]*}}, [[REG1]]
define signext i16 @asr_sext_i1_i16(i1 %b) {
+; CHECK-LABEL: asr_sext_i1_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sbfx w8, w0, #0, #1
+; CHECK-NEXT: sxth w0, w8
+; CHECK-NEXT: ret
%1 = sext i1 %b to i16
%2 = ashr i16 %1, 1
ret i16 %2
}
-; CHECK-LABEL: asr_zext_i1_i32
-; CHECK: mov {{w[0-9]*}}, wzr
define i32 @asr_zext_i1_i32(i1 %b) {
+; CHECK-LABEL: asr_zext_i1_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
%1 = zext i1 %b to i32
%2 = ashr i32 %1, 1
ret i32 %2
}
-; CHECK-LABEL: asr_sext_i1_i32
-; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #0, #1
define i32 @asr_sext_i1_i32(i1 %b) {
+; CHECK-LABEL: asr_sext_i1_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sbfx w0, w0, #0, #1
+; CHECK-NEXT: ret
%1 = sext i1 %b to i32
%2 = ashr i32 %1, 1
ret i32 %2
}
-; CHECK-LABEL: asr_zext_i1_i64
-; CHECK: mov {{x[0-9]*}}, xzr
define i64 @asr_zext_i1_i64(i1 %b) {
+; CHECK-LABEL: asr_zext_i1_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov x0, xzr
+; CHECK-NEXT: ret
%1 = zext i1 %b to i64
%2 = ashr i64 %1, 1
ret i64 %2
}
-; CHECK-LABEL: asr_sext_i1_i64
-; CHECK: sbfx {{x[0-9]*}}, {{x[0-9]*}}, #0, #1
define i64 @asr_sext_i1_i64(i1 %b) {
+; CHECK-LABEL: asr_sext_i1_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfx x0, x0, #0, #1
+; CHECK-NEXT: ret
%1 = sext i1 %b to i64
%2 = ashr i64 %1, 1
ret i64 %2
}
-; CHECK-LABEL: lsr_zext_i1_i16
-; CHECK: uxth {{w[0-9]*}}, wzr
define zeroext i16 @lsr_zext_i1_i16(i1 %b) {
+; CHECK-LABEL: lsr_zext_i1_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: uxth w0, wzr
+; CHECK-NEXT: ret
%1 = zext i1 %b to i16
%2 = lshr i16 %1, 1
ret i16 %2
}
-; CHECK-LABEL: lsr_sext_i1_i16
-; CHECK: sbfx [[REG1:w[0-9]+]], {{w[0-9]*}}, #0, #1
-; CHECK-NEXT: ubfx [[REG2:w[0-9]+]], [[REG1]], #1, #15
-; CHECK-NEXT: sxth {{w[0-9]*}}, [[REG2]]
define signext i16 @lsr_sext_i1_i16(i1 %b) {
+; CHECK-LABEL: lsr_sext_i1_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sbfx w8, w0, #0, #1
+; CHECK-NEXT: ubfx w8, w8, #1, #15
+; CHECK-NEXT: sxth w0, w8
+; CHECK-NEXT: ret
%1 = sext i1 %b to i16
%2 = lshr i16 %1, 1
ret i16 %2
}
-; CHECK-LABEL: lsr_zext_i1_i32
-; CHECK: mov {{w[0-9]*}}, wzr
define i32 @lsr_zext_i1_i32(i1 %b) {
+; CHECK-LABEL: lsr_zext_i1_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
%1 = zext i1 %b to i32
%2 = lshr i32 %1, 1
ret i32 %2
}
-; CHECK-LABEL: lsr_sext_i1_i32
-; CHECK: sbfx [[REG1:w[0-9]+]], {{w[0-9]*}}, #0, #1
-; CHECK-NEXT: lsr {{w[0-9]*}}, [[REG1:w[0-9]+]], #1
define i32 @lsr_sext_i1_i32(i1 %b) {
+; CHECK-LABEL: lsr_sext_i1_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sbfx w8, w0, #0, #1
+; CHECK-NEXT: lsr w0, w8, #1
+; CHECK-NEXT: ret
%1 = sext i1 %b to i32
%2 = lshr i32 %1, 1
ret i32 %2
}
-; CHECK-LABEL: lsr_zext_i1_i64
-; CHECK: mov {{x[0-9]*}}, xzr
define i64 @lsr_zext_i1_i64(i1 %b) {
+; CHECK-LABEL: lsr_zext_i1_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: mov x0, xzr
+; CHECK-NEXT: ret
%1 = zext i1 %b to i64
%2 = lshr i64 %1, 1
ret i64 %2
}
-; CHECK-LABEL: lsl_zext_i1_i16
-; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
define zeroext i16 @lsl_zext_i1_i16(i1 %b) {
+; CHECK-LABEL: lsl_zext_i1_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ubfiz w8, w0, #4, #1
+; CHECK-NEXT: uxth w0, w8
+; CHECK-NEXT: ret
%1 = zext i1 %b to i16
%2 = shl i16 %1, 4
ret i16 %2
}
-; CHECK-LABEL: lsl_sext_i1_i16
-; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
define signext i16 @lsl_sext_i1_i16(i1 %b) {
+; CHECK-LABEL: lsl_sext_i1_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sbfiz w8, w0, #4, #1
+; CHECK-NEXT: sxth w0, w8
+; CHECK-NEXT: ret
%1 = sext i1 %b to i16
%2 = shl i16 %1, 4
ret i16 %2
}
-; CHECK-LABEL: lsl_zext_i1_i32
-; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
define i32 @lsl_zext_i1_i32(i1 %b) {
+; CHECK-LABEL: lsl_zext_i1_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ubfiz w0, w0, #4, #1
+; CHECK-NEXT: ret
%1 = zext i1 %b to i32
%2 = shl i32 %1, 4
ret i32 %2
}
-; CHECK-LABEL: lsl_sext_i1_i32
-; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
define i32 @lsl_sext_i1_i32(i1 %b) {
+; CHECK-LABEL: lsl_sext_i1_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sbfiz w0, w0, #4, #1
+; CHECK-NEXT: ret
%1 = sext i1 %b to i32
%2 = shl i32 %1, 4
ret i32 %2
}
-; CHECK-LABEL: lsl_zext_i1_i64
-; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1
define i64 @lsl_zext_i1_i64(i1 %b) {
+; CHECK-LABEL: lsl_zext_i1_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: ubfiz x0, x0, #4, #1
+; CHECK-NEXT: ret
%1 = zext i1 %b to i64
%2 = shl i64 %1, 4
ret i64 %2
}
-; CHECK-LABEL: lsl_sext_i1_i64
-; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1
define i64 @lsl_sext_i1_i64(i1 %b) {
+; CHECK-LABEL: lsl_sext_i1_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfiz x0, x0, #4, #1
+; CHECK-NEXT: ret
%1 = sext i1 %b to i64
%2 = shl i64 %1, 4
ret i64 %2
}
-; CHECK-LABEL: lslv_i8
-; CHECK: and [[REG1:w[0-9]+]], w1, #0xff
-; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]]
-; CHECK-NEXT: and {{w[0-9]+}}, [[REG2]], #0xff
define zeroext i8 @lslv_i8(i8 %a, i8 %b) {
+; CHECK-LABEL: lslv_i8:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: and w8, w1, #0xff
+; CHECK-NEXT: lsl w8, w0, w8
+; CHECK-NEXT: and w8, w8, #0xff
+; CHECK-NEXT: uxtb w0, w8
+; CHECK-NEXT: ret
%1 = shl i8 %a, %b
ret i8 %1
}
-; CHECK-LABEL: lsl_i8
-; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
define zeroext i8 @lsl_i8(i8 %a) {
+; CHECK-LABEL: lsl_i8:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ubfiz w8, w0, #4, #4
+; CHECK-NEXT: uxtb w0, w8
+; CHECK-NEXT: ret
%1 = shl i8 %a, 4
ret i8 %1
}
-; CHECK-LABEL: lsl_zext_i8_i16
-; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
define zeroext i16 @lsl_zext_i8_i16(i8 %b) {
+; CHECK-LABEL: lsl_zext_i8_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ubfiz w8, w0, #4, #8
+; CHECK-NEXT: uxth w0, w8
+; CHECK-NEXT: ret
%1 = zext i8 %b to i16
%2 = shl i16 %1, 4
ret i16 %2
}
-; CHECK-LABEL: lsl_sext_i8_i16
-; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
define signext i16 @lsl_sext_i8_i16(i8 %b) {
+; CHECK-LABEL: lsl_sext_i8_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sbfiz w8, w0, #4, #8
+; CHECK-NEXT: sxth w0, w8
+; CHECK-NEXT: ret
%1 = sext i8 %b to i16
%2 = shl i16 %1, 4
ret i16 %2
}
-; CHECK-LABEL: lsl_zext_i8_i32
-; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
define i32 @lsl_zext_i8_i32(i8 %b) {
+; CHECK-LABEL: lsl_zext_i8_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ubfiz w0, w0, #4, #8
+; CHECK-NEXT: ret
%1 = zext i8 %b to i32
%2 = shl i32 %1, 4
ret i32 %2
}
-; CHECK-LABEL: lsl_sext_i8_i32
-; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
define i32 @lsl_sext_i8_i32(i8 %b) {
+; CHECK-LABEL: lsl_sext_i8_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sbfiz w0, w0, #4, #8
+; CHECK-NEXT: ret
%1 = sext i8 %b to i32
%2 = shl i32 %1, 4
ret i32 %2
}
-; CHECK-LABEL: lsl_zext_i8_i64
-; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #8
define i64 @lsl_zext_i8_i64(i8 %b) {
+; CHECK-LABEL: lsl_zext_i8_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: ubfiz x0, x0, #4, #8
+; CHECK-NEXT: ret
%1 = zext i8 %b to i64
%2 = shl i64 %1, 4
ret i64 %2
}
-; CHECK-LABEL: lsl_sext_i8_i64
-; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #8
define i64 @lsl_sext_i8_i64(i8 %b) {
+; CHECK-LABEL: lsl_sext_i8_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfiz x0, x0, #4, #8
+; CHECK-NEXT: ret
%1 = sext i8 %b to i64
%2 = shl i64 %1, 4
ret i64 %2
}
-; CHECK-LABEL: lslv_i16
-; CHECK: and [[REG1:w[0-9]+]], w1, #0xffff
-; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]]
-; CHECK-NEXT: and {{w[0-9]+}}, [[REG2]], #0xffff
define zeroext i16 @lslv_i16(i16 %a, i16 %b) {
+; CHECK-LABEL: lslv_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: and w8, w1, #0xffff
+; CHECK-NEXT: lsl w8, w0, w8
+; CHECK-NEXT: and w8, w8, #0xffff
+; CHECK-NEXT: uxth w0, w8
+; CHECK-NEXT: ret
%1 = shl i16 %a, %b
ret i16 %1
}
-; CHECK-LABEL: lsl_i16
-; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
define zeroext i16 @lsl_i16(i16 %a) {
+; CHECK-LABEL: lsl_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ubfiz w8, w0, #8, #8
+; CHECK-NEXT: uxth w0, w8
+; CHECK-NEXT: ret
%1 = shl i16 %a, 8
ret i16 %1
}
-; CHECK-LABEL: lsl_zext_i16_i32
-; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16
define i32 @lsl_zext_i16_i32(i16 %b) {
+; CHECK-LABEL: lsl_zext_i16_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ubfiz w0, w0, #8, #16
+; CHECK-NEXT: ret
%1 = zext i16 %b to i32
%2 = shl i32 %1, 8
ret i32 %2
}
-; CHECK-LABEL: lsl_sext_i16_i32
-; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16
define i32 @lsl_sext_i16_i32(i16 %b) {
+; CHECK-LABEL: lsl_sext_i16_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sbfiz w0, w0, #8, #16
+; CHECK-NEXT: ret
%1 = sext i16 %b to i32
%2 = shl i32 %1, 8
ret i32 %2
}
-; CHECK-LABEL: lsl_zext_i16_i64
-; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #8, #16
define i64 @lsl_zext_i16_i64(i16 %b) {
+; CHECK-LABEL: lsl_zext_i16_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: ubfiz x0, x0, #8, #16
+; CHECK-NEXT: ret
%1 = zext i16 %b to i64
%2 = shl i64 %1, 8
ret i64 %2
}
-; CHECK-LABEL: lsl_sext_i16_i64
-; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #8, #16
define i64 @lsl_sext_i16_i64(i16 %b) {
+; CHECK-LABEL: lsl_sext_i16_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfiz x0, x0, #8, #16
+; CHECK-NEXT: ret
%1 = sext i16 %b to i64
%2 = shl i64 %1, 8
ret i64 %2
}
-; CHECK-LABEL: lslv_i32
-; CHECK: lsl {{w[0-9]*}}, w0, w1
define zeroext i32 @lslv_i32(i32 %a, i32 %b) {
+; CHECK-LABEL: lslv_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: lsl w0, w0, w1
+; CHECK-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
-; CHECK-LABEL: lsl_i32
-; CHECK: lsl {{w[0-9]*}}, {{w[0-9]*}}, #16
define zeroext i32 @lsl_i32(i32 %a) {
+; CHECK-LABEL: lsl_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: lsl w0, w0, #16
+; CHECK-NEXT: ret
%1 = shl i32 %a, 16
ret i32 %1
}
-; CHECK-LABEL: lsl_zext_i32_i64
-; CHECK: ubfiz {{x[0-9]+}}, {{x[0-9]+}}, #16, #32
define i64 @lsl_zext_i32_i64(i32 %b) {
+; CHECK-LABEL: lsl_zext_i32_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: ubfiz x0, x0, #16, #32
+; CHECK-NEXT: ret
%1 = zext i32 %b to i64
%2 = shl i64 %1, 16
ret i64 %2
}
-; CHECK-LABEL: lsl_sext_i32_i64
-; CHECK: sbfiz {{x[0-9]+}}, {{x[0-9]+}}, #16, #32
define i64 @lsl_sext_i32_i64(i32 %b) {
+; CHECK-LABEL: lsl_sext_i32_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: sbfiz x0, x0, #16, #32
+; CHECK-NEXT: ret
%1 = sext i32 %b to i64
%2 = shl i64 %1, 16
ret i64 %2
}
-; CHECK-LABEL: lslv_i64
-; CHECK: lsl {{x[0-9]*}}, x0, x1
define i64 @lslv_i64(i64 %a, i64 %b) {
+; CHECK-LABEL: lslv_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: lsl x0, x0, x1
+; CHECK-NEXT: ret
%1 = shl i64 %a, %b
ret i64 %1
}
-; CHECK-LABEL: lsl_i64
-; CHECK: lsl {{x[0-9]*}}, {{x[0-9]*}}, #32
define i64 @lsl_i64(i64 %a) {
+; CHECK-LABEL: lsl_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: lsl x0, x0, #32
+; CHECK-NEXT: ret
%1 = shl i64 %a, 32
ret i64 %1
}
-; CHECK-LABEL: lsrv_i8
-; CHECK: and [[REG1:w[0-9]+]], w0, #0xff
-; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xff
-; CHECK-NEXT: lsr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
-; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xff
define zeroext i8 @lsrv_i8(i8 %a, i8 %b) {
+; CHECK-LABEL: lsrv_i8:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: and w8, w0, #0xff
+; CHECK-NEXT: and w9, w1, #0xff
+; CHECK-NEXT: lsr w8, w8, w9
+; CHECK-NEXT: and w8, w8, #0xff
+; CHECK-NEXT: uxtb w0, w8
+; CHECK-NEXT: ret
%1 = lshr i8 %a, %b
ret i8 %1
}
-; CHECK-LABEL: lsr_i8
-; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
define zeroext i8 @lsr_i8(i8 %a) {
+; CHECK-LABEL: lsr_i8:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ubfx w8, w0, #4, #4
+; CHECK-NEXT: uxtb w0, w8
+; CHECK-NEXT: ret
%1 = lshr i8 %a, 4
ret i8 %1
}
-; CHECK-LABEL: lsr_zext_i8_i16
-; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
define zeroext i16 @lsr_zext_i8_i16(i8 %b) {
+; CHECK-LABEL: lsr_zext_i8_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ubfx w8, w0, #4, #4
+; CHECK-NEXT: uxth w0, w8
+; CHECK-NEXT: ret
%1 = zext i8 %b to i16
%2 = lshr i16 %1, 4
ret i16 %2
}
-; CHECK-LABEL: lsr_sext_i8_i16
-; CHECK: sxtb [[REG:w[0-9]+]], w0
-; CHECK-NEXT: ubfx {{w[0-9]*}}, [[REG]], #4, #12
define signext i16 @lsr_sext_i8_i16(i8 %b) {
+; CHECK-LABEL: lsr_sext_i8_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sxtb w8, w0
+; CHECK-NEXT: ubfx w8, w8, #4, #12
+; CHECK-NEXT: sxth w0, w8
+; CHECK-NEXT: ret
%1 = sext i8 %b to i16
%2 = lshr i16 %1, 4
ret i16 %2
}
-; CHECK-LABEL: lsr_zext_i8_i32
-; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
define i32 @lsr_zext_i8_i32(i8 %b) {
+; CHECK-LABEL: lsr_zext_i8_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ubfx w0, w0, #4, #4
+; CHECK-NEXT: ret
%1 = zext i8 %b to i32
%2 = lshr i32 %1, 4
ret i32 %2
}
-; CHECK-LABEL: lsr_sext_i8_i32
-; CHECK: sxtb [[REG:w[0-9]+]], w0
-; CHECK-NEXT: lsr {{w[0-9]*}}, [[REG]], #4
define i32 @lsr_sext_i8_i32(i8 %b) {
+; CHECK-LABEL: lsr_sext_i8_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sxtb w8, w0
+; CHECK-NEXT: lsr w0, w8, #4
+; CHECK-NEXT: ret
%1 = sext i8 %b to i32
%2 = lshr i32 %1, 4
ret i32 %2
}
-; CHECK-LABEL: lsrv_i16
-; CHECK: and [[REG1:w[0-9]+]], w0, #0xffff
-; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xffff
-; CHECK-NEXT: lsr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
-; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xffff
define zeroext i16 @lsrv_i16(i16 %a, i16 %b) {
+; CHECK-LABEL: lsrv_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: and w8, w0, #0xffff
+; CHECK-NEXT: and w9, w1, #0xffff
+; CHECK-NEXT: lsr w8, w8, w9
+; CHECK-NEXT: and w8, w8, #0xffff
+; CHECK-NEXT: uxth w0, w8
+; CHECK-NEXT: ret
%1 = lshr i16 %a, %b
ret i16 %1
}
-; CHECK-LABEL: lsr_i16
-; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
define zeroext i16 @lsr_i16(i16 %a) {
+; CHECK-LABEL: lsr_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ubfx w8, w0, #8, #8
+; CHECK-NEXT: uxth w0, w8
+; CHECK-NEXT: ret
%1 = lshr i16 %a, 8
ret i16 %1
}
-; CHECK-LABEL: lsrv_i32
-; CHECK: lsr {{w[0-9]*}}, w0, w1
define zeroext i32 @lsrv_i32(i32 %a, i32 %b) {
+; CHECK-LABEL: lsrv_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: lsr w0, w0, w1
+; CHECK-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
-; CHECK-LABEL: lsr_i32
-; CHECK: lsr {{w[0-9]*}}, {{w[0-9]*}}, #16
define zeroext i32 @lsr_i32(i32 %a) {
+; CHECK-LABEL: lsr_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: lsr w0, w0, #16
+; CHECK-NEXT: ret
%1 = lshr i32 %a, 16
ret i32 %1
}
-; CHECK-LABEL: lsrv_i64
-; CHECK: lsr {{x[0-9]*}}, x0, x1
define i64 @lsrv_i64(i64 %a, i64 %b) {
+; CHECK-LABEL: lsrv_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: lsr x0, x0, x1
+; CHECK-NEXT: ret
%1 = lshr i64 %a, %b
ret i64 %1
}
-; CHECK-LABEL: lsr_i64
-; CHECK: lsr {{x[0-9]*}}, {{x[0-9]*}}, #32
define i64 @lsr_i64(i64 %a) {
+; CHECK-LABEL: lsr_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: lsr x0, x0, #32
+; CHECK-NEXT: ret
%1 = lshr i64 %a, 32
ret i64 %1
}
-; CHECK-LABEL: asrv_i8
-; CHECK: sxtb [[REG1:w[0-9]+]], w0
-; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xff
-; CHECK-NEXT: asr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
-; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xff
define zeroext i8 @asrv_i8(i8 %a, i8 %b) {
+; CHECK-LABEL: asrv_i8:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sxtb w8, w0
+; CHECK-NEXT: and w9, w1, #0xff
+; CHECK-NEXT: asr w8, w8, w9
+; CHECK-NEXT: and w8, w8, #0xff
+; CHECK-NEXT: uxtb w0, w8
+; CHECK-NEXT: ret
%1 = ashr i8 %a, %b
ret i8 %1
}
-; CHECK-LABEL: asr_i8
-; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
define zeroext i8 @asr_i8(i8 %a) {
+; CHECK-LABEL: asr_i8:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sbfx w8, w0, #4, #4
+; CHECK-NEXT: uxtb w0, w8
+; CHECK-NEXT: ret
%1 = ashr i8 %a, 4
ret i8 %1
}
-; CHECK-LABEL: asr_zext_i8_i16
-; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
define zeroext i16 @asr_zext_i8_i16(i8 %b) {
+; CHECK-LABEL: asr_zext_i8_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ubfx w8, w0, #4, #4
+; CHECK-NEXT: uxth w0, w8
+; CHECK-NEXT: ret
%1 = zext i8 %b to i16
%2 = ashr i16 %1, 4
ret i16 %2
}
-; CHECK-LABEL: asr_sext_i8_i16
-; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
define signext i16 @asr_sext_i8_i16(i8 %b) {
+; CHECK-LABEL: asr_sext_i8_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sbfx w8, w0, #4, #4
+; CHECK-NEXT: sxth w0, w8
+; CHECK-NEXT: ret
%1 = sext i8 %b to i16
%2 = ashr i16 %1, 4
ret i16 %2
}
-; CHECK-LABEL: asr_zext_i8_i32
-; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
define i32 @asr_zext_i8_i32(i8 %b) {
+; CHECK-LABEL: asr_zext_i8_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ubfx w0, w0, #4, #4
+; CHECK-NEXT: ret
%1 = zext i8 %b to i32
%2 = ashr i32 %1, 4
ret i32 %2
}
-; CHECK-LABEL: asr_sext_i8_i32
-; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
define i32 @asr_sext_i8_i32(i8 %b) {
+; CHECK-LABEL: asr_sext_i8_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sbfx w0, w0, #4, #4
+; CHECK-NEXT: ret
%1 = sext i8 %b to i32
%2 = ashr i32 %1, 4
ret i32 %2
}
-; CHECK-LABEL: asrv_i16
-; CHECK: sxth [[REG1:w[0-9]+]], w0
-; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xffff
-; CHECK-NEXT: asr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
-; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xffff
define zeroext i16 @asrv_i16(i16 %a, i16 %b) {
+; CHECK-LABEL: asrv_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sxth w8, w0
+; CHECK-NEXT: and w9, w1, #0xffff
+; CHECK-NEXT: asr w8, w8, w9
+; CHECK-NEXT: and w8, w8, #0xffff
+; CHECK-NEXT: uxth w0, w8
+; CHECK-NEXT: ret
%1 = ashr i16 %a, %b
ret i16 %1
}
-; CHECK-LABEL: asr_i16
-; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
define zeroext i16 @asr_i16(i16 %a) {
+; CHECK-LABEL: asr_i16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: sbfx w8, w0, #8, #8
+; CHECK-NEXT: uxth w0, w8
+; CHECK-NEXT: ret
%1 = ashr i16 %a, 8
ret i16 %1
}
-; CHECK-LABEL: asrv_i32
-; CHECK: asr {{w[0-9]*}}, w0, w1
define zeroext i32 @asrv_i32(i32 %a, i32 %b) {
+; CHECK-LABEL: asrv_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: asr w0, w0, w1
+; CHECK-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
-; CHECK-LABEL: asr_i32
-; CHECK: asr {{w[0-9]*}}, {{w[0-9]*}}, #16
define zeroext i32 @asr_i32(i32 %a) {
+; CHECK-LABEL: asr_i32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: asr w0, w0, #16
+; CHECK-NEXT: ret
%1 = ashr i32 %a, 16
ret i32 %1
}
-; CHECK-LABEL: asrv_i64
-; CHECK: asr {{x[0-9]*}}, x0, x1
define i64 @asrv_i64(i64 %a, i64 %b) {
+; CHECK-LABEL: asrv_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: asr x0, x0, x1
+; CHECK-NEXT: ret
%1 = ashr i64 %a, %b
ret i64 %1
}
-; CHECK-LABEL: asr_i64
-; CHECK: asr {{x[0-9]*}}, {{x[0-9]*}}, #32
define i64 @asr_i64(i64 %a) {
+; CHECK-LABEL: asr_i64:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: asr x0, x0, #32
+; CHECK-NEXT: ret
%1 = ashr i64 %a, 32
ret i64 %1
}
-; CHECK-LABEL: shift_test1
-; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
-; CHECK-NEXT: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
define i32 @shift_test1(i8 %a) {
+; CHECK-LABEL: shift_test1:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ubfiz w8, w0, #4, #4
+; CHECK-NEXT: sbfx w8, w8, #4, #4
+; CHECK-NEXT: sxtb w0, w8
+; CHECK-NEXT: ret
%1 = shl i8 %a, 4
%2 = ashr i8 %1, 4
%3 = sext i8 %2 to i32
@@ -498,46 +653,58 @@ define i32 @shift_test1(i8 %a) {
; Test zero shifts
-; CHECK-LABEL: shl_zero
-; CHECK-NOT: lsl
define i32 @shl_zero(i32 %a) {
+; CHECK-LABEL: shl_zero:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ret
%1 = shl i32 %a, 0
ret i32 %1
}
-; CHECK-LABEL: lshr_zero
-; CHECK-NOT: lsr
define i32 @lshr_zero(i32 %a) {
+; CHECK-LABEL: lshr_zero:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ret
%1 = lshr i32 %a, 0
ret i32 %1
}
-; CHECK-LABEL: ashr_zero
-; CHECK-NOT: asr
define i32 @ashr_zero(i32 %a) {
+; CHECK-LABEL: ashr_zero:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ret
%1 = ashr i32 %a, 0
ret i32 %1
}
-; CHECK-LABEL: shl_zext_zero
-; CHECK: ubfx x0, x0, #0, #32
define i64 @shl_zext_zero(i32 %a) {
+; CHECK-LABEL: shl_zext_zero:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: ubfx x0, x0, #0, #32
+; CHECK-NEXT: ret
%1 = zext i32 %a to i64
%2 = shl i64 %1, 0
ret i64 %2
}
-; CHECK-LABEL: lshr_zext_zero
-; CHECK: ubfx x0, x0, #0, #32
define i64 @lshr_zext_zero(i32 %a) {
+; CHECK-LABEL: lshr_zext_zero:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: ubfx x0, x0, #0, #32
+; CHECK-NEXT: ret
%1 = zext i32 %a to i64
%2 = lshr i64 %1, 0
ret i64 %2
}
-; CHECK-LABEL: ashr_zext_zero
-; CHECK: ubfx x0, x0, #0, #32
define i64 @ashr_zext_zero(i32 %a) {
+; CHECK-LABEL: ashr_zext_zero:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: ; kill: def $w0 killed $w0 def $x0
+; CHECK-NEXT: ubfx x0, x0, #0, #32
+; CHECK-NEXT: ret
%1 = zext i32 %a to i64
%2 = ashr i64 %1, 0
ret i64 %2
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