[PATCH] D111135: [AArch64][SVE] Improve VECTOR_SPLICE codegen for VL > 128-bit

[Bradley Smith via Phabricator via llvm-commits]

bsmith updated this revision to Diff 377280.
bsmith retitled this revision from "[AArch64][SVE] Improve VECTOR_SPLICE codegen when vector length is known" to "[AArch64][SVE] Improve VECTOR_SPLICE codegen for VL > 128-bit".
bsmith added a comment.

- Move idx==0 optimization to getNode
- Allow lowering for all VL lengths, not just the current one.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111135/new/

https://reviews.llvm.org/D111135

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

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