[PATCH] D111135: [AArch64][SVE] Improve VECTOR_SPLICE codegen when vector length is known

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7642
+
+  if (Idx.sge(-1) && Idx.slt(Ty.getVectorMinNumElements() * MinSVEBlocks))
     return Op;
----------------
bsmith wrote:
> paulwalker-arm wrote:
> > getMinSVEVectorSizeInBits doesn't look relevant here.  The restriction is linked to our expected isel to either INSR or EXT instructions.  So I think we can be explicit here and use `2048/Ty.getVectorElementType().getSizeInBits()` along with a suitable comment about the range of EXT's index operand.
> Is that really correct? If we just allow all vector sizes then surely you would end up with incorrect ext instructions? For example, if you had a VL of 128, a splice of a `<vscale x 16 x i8>`  with an index of 31 would give an ext with an immediate of 31, which is only correct if your VL is >= 256, or are you suggesting that such a DAG node is malformed and hence undef?
The latter.  We can assume the index in range and just need to ensure that when out of range we don't do anything bad (like access random memory).  In our case we'll always emit an EXT instruction that will either do the correct thing when the index is in range (i.e. the defined case) or return the first vector when the index is out of range (i.e. the undefined case).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111135/new/

https://reviews.llvm.org/D111135