[PATCH] D111135: [AArch64][SVE] Improve VECTOR_SPLICE codegen when vector length is known

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7639-7640
+
+  if (Idx == 0)
+    return Op1;
+
----------------
I think this is better done within getNode() so as to eliminate the possibility as early as possible.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7642
+
+  if (Idx.sge(-1) && Idx.slt(Ty.getVectorMinNumElements() * MinSVEBlocks))
     return Op;
----------------
getMinSVEVectorSizeInBits doesn't look relevant here.  The restriction is linked to our expected isel to either INSR or EXT instructions.  So I think we can be explicit here and use `2048/Ty.getVectorElementType().getSizeInBits()` along with a suitable comment about the range of EXT's index operand.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111135/new/

https://reviews.llvm.org/D111135