[PATCH] D111093: [X86][Costmodel] Load/store i64/f64 Stride=6 VF=4 interleaving costs
Roman Lebedev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 5 07:00:52 PDT 2021
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe2784c5d8cf6: [X86][Costmodel] Load/store i64/f64 Stride=6 VF=4 interleaving costs (authored by lebedev.ri).
Changed prior to commit:
https://reviews.llvm.org/D111093?vs=377002&id=377219#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D111093/new/
https://reviews.llvm.org/D111093
Files:
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
Index: llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
@@ -23,7 +23,7 @@
;
; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store i64 %v5, i64* %out5, align 8
; AVX2: LV: Found an estimated cost of 11 for VF 2 For instruction: store i64 %v5, i64* %out5, align 8
-; AVX2: LV: Found an estimated cost of 78 for VF 4 For instruction: store i64 %v5, i64* %out5, align 8
+; AVX2: LV: Found an estimated cost of 21 for VF 4 For instruction: store i64 %v5, i64* %out5, align 8
; AVX2: LV: Found an estimated cost of 156 for VF 8 For instruction: store i64 %v5, i64* %out5, align 8
;
; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: store i64 %v5, i64* %out5, align 8
Index: llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
@@ -23,7 +23,7 @@
;
; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store double %v5, double* %out5, align 8
; AVX2: LV: Found an estimated cost of 11 for VF 2 For instruction: store double %v5, double* %out5, align 8
-; AVX2: LV: Found an estimated cost of 54 for VF 4 For instruction: store double %v5, double* %out5, align 8
+; AVX2: LV: Found an estimated cost of 21 for VF 4 For instruction: store double %v5, double* %out5, align 8
; AVX2: LV: Found an estimated cost of 108 for VF 8 For instruction: store double %v5, double* %out5, align 8
;
; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: store double %v5, double* %out5, align 8
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
@@ -23,7 +23,7 @@
;
; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i64, i64* %in0, align 8
; AVX2: LV: Found an estimated cost of 9 for VF 2 For instruction: %v0 = load i64, i64* %in0, align 8
-; AVX2: LV: Found an estimated cost of 78 for VF 4 For instruction: %v0 = load i64, i64* %in0, align 8
+; AVX2: LV: Found an estimated cost of 24 for VF 4 For instruction: %v0 = load i64, i64* %in0, align 8
; AVX2: LV: Found an estimated cost of 156 for VF 8 For instruction: %v0 = load i64, i64* %in0, align 8
;
; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i64, i64* %in0, align 8
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
@@ -23,7 +23,7 @@
;
; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load double, double* %in0, align 8
; AVX2: LV: Found an estimated cost of 9 for VF 2 For instruction: %v0 = load double, double* %in0, align 8
-; AVX2: LV: Found an estimated cost of 48 for VF 4 For instruction: %v0 = load double, double* %in0, align 8
+; AVX2: LV: Found an estimated cost of 24 for VF 4 For instruction: %v0 = load double, double* %in0, align 8
; AVX2: LV: Found an estimated cost of 96 for VF 8 For instruction: %v0 = load double, double* %in0, align 8
;
; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load double, double* %in0, align 8
Index: llvm/lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -5154,6 +5154,7 @@
{6, MVT::v16i32, 64}, // (load 96i32 and) deinterleave into 6 x 16i32
{6, MVT::v2i64, 6}, // (load 12i64 and) deinterleave into 6 x 2i64
+ {6, MVT::v4i64, 18}, // (load 24i64 and) deinterleave into 6 x 4i64
{8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32
};
@@ -5242,6 +5243,7 @@
{6, MVT::v16i32, 66}, // interleave 6 x 16i32 into 96i32 (and store)
{6, MVT::v2i64, 8}, // interleave 6 x 2i64 into 12i64 (and store)
+ {6, MVT::v4i64, 15}, // interleave 6 x 4i64 into 24i64 (and store)
};
if (Opcode == Instruction::Load) {
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