[PATCH] D111091: [X86][Costmodel] Load/store i32/f32 Stride=6 VF=16 interleaving costs

[Roman Lebedev via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG79d6d12d9585: [X86][Costmodel] Load/store i32/f32 Stride=6 VF=16 interleaving costs (authored by lebedev.ri).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111091/new/

https://reviews.llvm.org/D111091

Files:
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll


Index: llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 11 for VF 2 For instruction:   store i32 %v5, i32* %out5, align 4
 ; AVX2: LV: Found an estimated cost of 15 for VF 4 For instruction:   store i32 %v5, i32* %out5, align 4
 ; AVX2: LV: Found an estimated cost of 39 for VF 8 For instruction:   store i32 %v5, i32* %out5, align 4
-; AVX2: LV: Found an estimated cost of 276 for VF 16 For instruction:   store i32 %v5, i32* %out5, align 4
+; AVX2: LV: Found an estimated cost of 78 for VF 16 For instruction:   store i32 %v5, i32* %out5, align 4
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   store i32 %v5, i32* %out5, align 4
 ; AVX512: LV: Found an estimated cost of 8 for VF 2 For instruction:   store i32 %v5, i32* %out5, align 4
Index: llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 11 for VF 2 For instruction:   store float %v5, float* %out5, align 4
 ; AVX2: LV: Found an estimated cost of 15 for VF 4 For instruction:   store float %v5, float* %out5, align 4
 ; AVX2: LV: Found an estimated cost of 39 for VF 8 For instruction:   store float %v5, float* %out5, align 4
-; AVX2: LV: Found an estimated cost of 228 for VF 16 For instruction:   store float %v5, float* %out5, align 4
+; AVX2: LV: Found an estimated cost of 78 for VF 16 For instruction:   store float %v5, float* %out5, align 4
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   store float %v5, float* %out5, align 4
 ; AVX512: LV: Found an estimated cost of 8 for VF 2 For instruction:   store float %v5, float* %out5, align 4
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 8 for VF 2 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 18 for VF 4 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 37 for VF 8 For instruction:   %v0 = load i32, i32* %in0, align 4
-; AVX2: LV: Found an estimated cost of 276 for VF 16 For instruction:   %v0 = load i32, i32* %in0, align 4
+; AVX2: LV: Found an estimated cost of 76 for VF 16 For instruction:   %v0 = load i32, i32* %in0, align 4
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load i32, i32* %in0, align 4
 ; AVX512: LV: Found an estimated cost of 7 for VF 2 For instruction:   %v0 = load i32, i32* %in0, align 4
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 8 for VF 2 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 18 for VF 4 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX2: LV: Found an estimated cost of 37 for VF 8 For instruction:   %v0 = load float, float* %in0, align 4
-; AVX2: LV: Found an estimated cost of 228 for VF 16 For instruction:   %v0 = load float, float* %in0, align 4
+; AVX2: LV: Found an estimated cost of 76 for VF 16 For instruction:   %v0 = load float, float* %in0, align 4
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load float, float* %in0, align 4
 ; AVX512: LV: Found an estimated cost of 7 for VF 2 For instruction:   %v0 = load float, float* %in0, align 4
Index: llvm/lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -5151,6 +5151,7 @@
       {6, MVT::v2i32, 6}, // (load 12i32 and) deinterleave into 6 x 2i32
       {6, MVT::v4i32, 15}, // (load 24i32 and) deinterleave into 6 x 4i32
       {6, MVT::v8i32, 31}, // (load 48i32 and) deinterleave into 6 x 8i32
+      {6, MVT::v16i32, 64}, // (load 96i32 and) deinterleave into 6 x 16i32
 
       {8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32
   };
@@ -5236,6 +5237,7 @@
       {6, MVT::v2i32, 9},  // interleave 6 x 2i32 into 12i32 (and store)
       {6, MVT::v4i32, 12},  // interleave 6 x 4i32 into 24i32 (and store)
       {6, MVT::v8i32, 33},  // interleave 6 x 8i32 into 48i32 (and store)
+      {6, MVT::v16i32, 66},  // interleave 6 x 16i32 into 96i32 (and store)
   };
 
   if (Opcode == Instruction::Load) {


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