[llvm] 3960693 - [X86][Costmodel] Load/store i64/f64 Stride=6 VF=2 interleaving costs
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 5 07:00:10 PDT 2021
Author: Roman Lebedev
Date: 2021-10-05T16:58:58+03:00
New Revision: 3960693048a067e295d25c252b5f3a985c637bf2
URL: https://github.com/llvm/llvm-project/commit/3960693048a067e295d25c252b5f3a985c637bf2
DIFF: https://github.com/llvm/llvm-project/commit/3960693048a067e295d25c252b5f3a985c637bf2.diff
LOG: [X86][Costmodel] Load/store i64/f64 Stride=6 VF=2 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/onese7rec - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: =3.0`
So could pick cost of `6`.
For store we have:
https://godbolt.org/z/bMd7dddnT - for intels `Block RThroughput: =8.0`; for ryzens, `Block RThroughput: <=6.0`
So we could pick cost of `8`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111092
Added:
Modified:
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 0128f2310ff6..02fa0a2159bc 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -5153,6 +5153,8 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
{6, MVT::v8i32, 31}, // (load 48i32 and) deinterleave into 6 x 8i32
{6, MVT::v16i32, 64}, // (load 96i32 and) deinterleave into 6 x 16i32
+ {6, MVT::v2i64, 6}, // (load 12i64 and) deinterleave into 6 x 2i64
+
{8, MVT::v8i32, 40} // (load 64i32 and) deinterleave into 8 x 8i32
};
@@ -5238,6 +5240,8 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
{6, MVT::v4i32, 12}, // interleave 6 x 4i32 into 24i32 (and store)
{6, MVT::v8i32, 33}, // interleave 6 x 8i32 into 48i32 (and store)
{6, MVT::v16i32, 66}, // interleave 6 x 16i32 into 96i32 (and store)
+
+ {6, MVT::v2i64, 8}, // interleave 6 x 2i64 into 12i64 (and store)
};
if (Opcode == Instruction::Load) {
diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
index 9ff11c8427f6..8974df4d143f 100644
--- a/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
+++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
@@ -22,7 +22,7 @@ target triple = "x86_64-unknown-linux-gnu"
; AVX1: LV: Found an estimated cost of 96 for VF 8 For instruction: %v0 = load double, double* %in0, align 8
;
; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load double, double* %in0, align 8
-; AVX2: LV: Found an estimated cost of 21 for VF 2 For instruction: %v0 = load double, double* %in0, align 8
+; AVX2: LV: Found an estimated cost of 9 for VF 2 For instruction: %v0 = load double, double* %in0, align 8
; AVX2: LV: Found an estimated cost of 48 for VF 4 For instruction: %v0 = load double, double* %in0, align 8
; AVX2: LV: Found an estimated cost of 96 for VF 8 For instruction: %v0 = load double, double* %in0, align 8
;
diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
index 2e586d7d11f4..688c8ff9f9db 100644
--- a/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
+++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
@@ -22,7 +22,7 @@ target triple = "x86_64-unknown-linux-gnu"
; AVX1: LV: Found an estimated cost of 156 for VF 8 For instruction: %v0 = load i64, i64* %in0, align 8
;
; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i64, i64* %in0, align 8
-; AVX2: LV: Found an estimated cost of 33 for VF 2 For instruction: %v0 = load i64, i64* %in0, align 8
+; AVX2: LV: Found an estimated cost of 9 for VF 2 For instruction: %v0 = load i64, i64* %in0, align 8
; AVX2: LV: Found an estimated cost of 78 for VF 4 For instruction: %v0 = load i64, i64* %in0, align 8
; AVX2: LV: Found an estimated cost of 156 for VF 8 For instruction: %v0 = load i64, i64* %in0, align 8
;
diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
index 8e1f9a7aa9c3..97c4538ed124 100644
--- a/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
+++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
@@ -22,7 +22,7 @@ target triple = "x86_64-unknown-linux-gnu"
; AVX1: LV: Found an estimated cost of 108 for VF 8 For instruction: store double %v5, double* %out5, align 8
;
; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store double %v5, double* %out5, align 8
-; AVX2: LV: Found an estimated cost of 21 for VF 2 For instruction: store double %v5, double* %out5, align 8
+; AVX2: LV: Found an estimated cost of 11 for VF 2 For instruction: store double %v5, double* %out5, align 8
; AVX2: LV: Found an estimated cost of 54 for VF 4 For instruction: store double %v5, double* %out5, align 8
; AVX2: LV: Found an estimated cost of 108 for VF 8 For instruction: store double %v5, double* %out5, align 8
;
diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
index 1a1b9ca555fc..e7170d85c8bf 100644
--- a/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
+++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
@@ -22,7 +22,7 @@ target triple = "x86_64-unknown-linux-gnu"
; AVX1: LV: Found an estimated cost of 156 for VF 8 For instruction: store i64 %v5, i64* %out5, align 8
;
; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store i64 %v5, i64* %out5, align 8
-; AVX2: LV: Found an estimated cost of 33 for VF 2 For instruction: store i64 %v5, i64* %out5, align 8
+; AVX2: LV: Found an estimated cost of 11 for VF 2 For instruction: store i64 %v5, i64* %out5, align 8
; AVX2: LV: Found an estimated cost of 78 for VF 4 For instruction: store i64 %v5, i64* %out5, align 8
; AVX2: LV: Found an estimated cost of 156 for VF 8 For instruction: store i64 %v5, i64* %out5, align 8
;
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