[llvm] 80a6456 - [RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.
Hsiangkai Wang via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 5 06:51:41 PDT 2021
Author: Hsiangkai Wang
Date: 2021-10-05T21:49:54+08:00
New Revision: 80a645630660b1096aa16e18ed4747b24995f6cb
URL: https://github.com/llvm/llvm-project/commit/80a645630660b1096aa16e18ed4747b24995f6cb
DIFF: https://github.com/llvm/llvm-project/commit/80a645630660b1096aa16e18ed4747b24995f6cb.diff
LOG: [RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.
vle1.v -> vlm.v
vse1.v -> vsm.v
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D106044
Added:
llvm/test/CodeGen/RISCV/rvv/vlm-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vlm-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll
Modified:
clang/include/clang/Basic/riscv_vector.td
clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
llvm/test/CodeGen/RISCV/rvv/load-mask.ll
llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
llvm/test/MC/RISCV/rvv/aliases.s
llvm/test/MC/RISCV/rvv/load.s
llvm/test/MC/RISCV/rvv/store.s
Removed:
llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll
llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll
################################################################################
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 25e583baf1565..8fed6cf30c561 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -588,8 +588,8 @@ let HasNoMaskedOverloaded = false,
Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
}] in {
class RVVVLEMaskBuiltin : RVVBuiltin<"m", "mPCUe", "c"> {
- let Name = "vle1_v";
- let IRName = "vle1";
+ let Name = "vlm_v";
+ let IRName = "vlm";
let HasMask = false;
}
}
@@ -735,8 +735,8 @@ let HasMaskedOffOperand = false,
IntrinsicTypes = {Ops[0]->getType(), Ops[3]->getType()};
}] in {
class RVVVSEMaskBuiltin : RVVBuiltin<"m", "0PUem", "c"> {
- let Name = "vse1_v";
- let IRName = "vse1";
+ let Name = "vsm_v";
+ let IRName = "vsm";
let HasMask = false;
}
}
@@ -1553,13 +1553,13 @@ let HasVL = false,
// 7. Vector Loads and Stores
// 7.4. Vector Unit-Stride Instructions
-def vle1: RVVVLEMaskBuiltin;
+def vlm: RVVVLEMaskBuiltin;
defm vle8: RVVVLEBuiltin<["c"]>;
defm vle16: RVVVLEBuiltin<["s","x"]>;
defm vle32: RVVVLEBuiltin<["i","f"]>;
defm vle64: RVVVLEBuiltin<["l","d"]>;
-def vse1 : RVVVSEMaskBuiltin;
+def vsm : RVVVSEMaskBuiltin;
defm vse8 : RVVVSEBuiltin<["c"]>;
defm vse16: RVVVSEBuiltin<["s","x"]>;
defm vse32: RVVVSEBuiltin<["i","f"]>;
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c
index 8f59c29f2f395..440025667a05c 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c
@@ -1187,72 +1187,72 @@ void test_vse64_v_f64m8_m (vbool8_t mask, double *base, vfloat64m8_t value, size
return vse64(mask, base, value, vl);
}
-// CHECK-RV64-LABEL: @test_vse1_v_b1(
+// CHECK-RV64-LABEL: @test_vsm_v_b1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i1>*
-// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv64i1.i64(<vscale x 64 x i1> [[VALUE:%.*]], <vscale x 64 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv64i1.i64(<vscale x 64 x i1> [[VALUE:%.*]], <vscale x 64 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
-void test_vse1_v_b1(uint8_t *base, vbool1_t value, size_t vl) {
- return vse1(base, value, vl);
+void test_vsm_v_b1(uint8_t *base, vbool1_t value, size_t vl) {
+ return vsm(base, value, vl);
}
-// CHECK-RV64-LABEL: @test_vse1_v_b2(
+// CHECK-RV64-LABEL: @test_vsm_v_b2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i1>*
-// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv32i1.i64(<vscale x 32 x i1> [[VALUE:%.*]], <vscale x 32 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv32i1.i64(<vscale x 32 x i1> [[VALUE:%.*]], <vscale x 32 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
-void test_vse1_v_b2(uint8_t *base, vbool2_t value, size_t vl) {
- return vse1(base, value, vl);
+void test_vsm_v_b2(uint8_t *base, vbool2_t value, size_t vl) {
+ return vsm(base, value, vl);
}
-// CHECK-RV64-LABEL: @test_vse1_v_b4(
+// CHECK-RV64-LABEL: @test_vsm_v_b4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i1>*
-// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv16i1.i64(<vscale x 16 x i1> [[VALUE:%.*]], <vscale x 16 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv16i1.i64(<vscale x 16 x i1> [[VALUE:%.*]], <vscale x 16 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
-void test_vse1_v_b4(uint8_t *base, vbool4_t value, size_t vl) {
- return vse1(base, value, vl);
+void test_vsm_v_b4(uint8_t *base, vbool4_t value, size_t vl) {
+ return vsm(base, value, vl);
}
-// CHECK-RV64-LABEL: @test_vse1_v_b8(
+// CHECK-RV64-LABEL: @test_vsm_v_b8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i1>*
-// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv8i1.i64(<vscale x 8 x i1> [[VALUE:%.*]], <vscale x 8 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv8i1.i64(<vscale x 8 x i1> [[VALUE:%.*]], <vscale x 8 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
-void test_vse1_v_b8(uint8_t *base, vbool8_t value, size_t vl) {
- return vse1(base, value, vl);
+void test_vsm_v_b8(uint8_t *base, vbool8_t value, size_t vl) {
+ return vsm(base, value, vl);
}
-// CHECK-RV64-LABEL: @test_vse1_v_b16(
+// CHECK-RV64-LABEL: @test_vsm_v_b16(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i1>*
-// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv4i1.i64(<vscale x 4 x i1> [[VALUE:%.*]], <vscale x 4 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv4i1.i64(<vscale x 4 x i1> [[VALUE:%.*]], <vscale x 4 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
-void test_vse1_v_b16(uint8_t *base, vbool16_t value, size_t vl) {
- return vse1(base, value, vl);
+void test_vsm_v_b16(uint8_t *base, vbool16_t value, size_t vl) {
+ return vsm(base, value, vl);
}
-// CHECK-RV64-LABEL: @test_vse1_v_b32(
+// CHECK-RV64-LABEL: @test_vsm_v_b32(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i1>*
-// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv2i1.i64(<vscale x 2 x i1> [[VALUE:%.*]], <vscale x 2 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv2i1.i64(<vscale x 2 x i1> [[VALUE:%.*]], <vscale x 2 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
-void test_vse1_v_b32(uint8_t *base, vbool32_t value, size_t vl) {
- return vse1(base, value, vl);
+void test_vsm_v_b32(uint8_t *base, vbool32_t value, size_t vl) {
+ return vsm(base, value, vl);
}
-// CHECK-RV64-LABEL: @test_vse1_v_b64(
+// CHECK-RV64-LABEL: @test_vsm_v_b64(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i1>*
-// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv1i1.i64(<vscale x 1 x i1> [[VALUE:%.*]], <vscale x 1 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv1i1.i64(<vscale x 1 x i1> [[VALUE:%.*]], <vscale x 1 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
-void test_vse1_v_b64(uint8_t *base, vbool64_t value, size_t vl) {
- return vse1(base, value, vl);
+void test_vsm_v_b64(uint8_t *base, vbool64_t value, size_t vl) {
+ return vsm(base, value, vl);
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
index bda35be396c91..e86fc960d7616 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
@@ -1776,3 +1776,72 @@ vfloat64m4_t test_vle64_v_f64m4_mt(vbool16_t mask, vfloat64m4_t maskedoff, const
vfloat64m8_t test_vle64_v_f64m8_mt(vbool8_t mask, vfloat64m8_t maskedoff, const double *base, size_t vl, uint8_t ta) {
return vle64_v_f64m8_mt(mask, maskedoff, base, vl, VE_TAIL_AGNOSTIC);
}
+
+// CHECK-RV64-LABEL: @test_vlm_v_b1(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i1>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1.i64(<vscale x 64 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP1]]
+//
+vbool1_t test_vlm_v_b1(const uint8_t *base, size_t vl) {
+ return vlm_v_b1(base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlm_v_b2(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i1>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1.i64(<vscale x 32 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP1]]
+//
+vbool2_t test_vlm_v_b2(const uint8_t *base, size_t vl) {
+ return vlm_v_b2(base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlm_v_b4(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i1>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1.i64(<vscale x 16 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP1]]
+//
+vbool4_t test_vlm_v_b4(const uint8_t *base, size_t vl) {
+ return vlm_v_b4(base, vl);
+}
+// CHECK-RV64-LABEL: @test_vlm_v_b8(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i1>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1.i64(<vscale x 8 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP1]]
+//
+vbool8_t test_vlm_v_b8(const uint8_t *base, size_t vl) {
+ return vlm_v_b8(base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlm_v_b16(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i1>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1.i64(<vscale x 4 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP1]]
+//
+vbool16_t test_vlm_v_b16(const uint8_t *base, size_t vl) {
+ return vlm_v_b16(base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlm_v_b32(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i1>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1.i64(<vscale x 2 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP1]]
+//
+vbool32_t test_vlm_v_b32(const uint8_t *base, size_t vl) {
+ return vlm_v_b32(base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vlm_v_b64(
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i1>*
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1.i64(<vscale x 1 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP1]]
+//
+vbool64_t test_vlm_v_b64(const uint8_t *base, size_t vl) {
+ return vlm_v_b64(base, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
index 0e80bb1513baa..b8d741b64fd85 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
@@ -1187,72 +1187,72 @@ void test_vse64_v_f64m8_m(vbool8_t mask, double *base, vfloat64m8_t value, size_
return vse64_v_f64m8_m(mask, base, value, vl);
}
-// CHECK-RV64-LABEL: @test_vse1_v_b1(
+// CHECK-RV64-LABEL: @test_vsm_v_b1(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i1>*
-// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv64i1.i64(<vscale x 64 x i1> [[VALUE:%.*]], <vscale x 64 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv64i1.i64(<vscale x 64 x i1> [[VALUE:%.*]], <vscale x 64 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
-void test_vse1_v_b1(uint8_t *base, vbool1_t value, size_t vl) {
- return vse1_v_b1(base, value, vl);
+void test_vsm_v_b1(uint8_t *base, vbool1_t value, size_t vl) {
+ return vsm_v_b1(base, value, vl);
}
-// CHECK-RV64-LABEL: @test_vse1_v_b2(
+// CHECK-RV64-LABEL: @test_vsm_v_b2(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i1>*
-// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv32i1.i64(<vscale x 32 x i1> [[VALUE:%.*]], <vscale x 32 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv32i1.i64(<vscale x 32 x i1> [[VALUE:%.*]], <vscale x 32 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
-void test_vse1_v_b2(uint8_t *base, vbool2_t value, size_t vl) {
- return vse1_v_b2(base, value, vl);
+void test_vsm_v_b2(uint8_t *base, vbool2_t value, size_t vl) {
+ return vsm_v_b2(base, value, vl);
}
-// CHECK-RV64-LABEL: @test_vse1_v_b4(
+// CHECK-RV64-LABEL: @test_vsm_v_b4(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i1>*
-// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv16i1.i64(<vscale x 16 x i1> [[VALUE:%.*]], <vscale x 16 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv16i1.i64(<vscale x 16 x i1> [[VALUE:%.*]], <vscale x 16 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
-void test_vse1_v_b4(uint8_t *base, vbool4_t value, size_t vl) {
- return vse1_v_b4(base, value, vl);
+void test_vsm_v_b4(uint8_t *base, vbool4_t value, size_t vl) {
+ return vsm_v_b4(base, value, vl);
}
-// CHECK-RV64-LABEL: @test_vse1_v_b8(
+// CHECK-RV64-LABEL: @test_vsm_v_b8(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i1>*
-// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv8i1.i64(<vscale x 8 x i1> [[VALUE:%.*]], <vscale x 8 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv8i1.i64(<vscale x 8 x i1> [[VALUE:%.*]], <vscale x 8 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
-void test_vse1_v_b8(uint8_t *base, vbool8_t value, size_t vl) {
- return vse1_v_b8(base, value, vl);
+void test_vsm_v_b8(uint8_t *base, vbool8_t value, size_t vl) {
+ return vsm_v_b8(base, value, vl);
}
-// CHECK-RV64-LABEL: @test_vse1_v_b16(
+// CHECK-RV64-LABEL: @test_vsm_v_b16(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i1>*
-// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv4i1.i64(<vscale x 4 x i1> [[VALUE:%.*]], <vscale x 4 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv4i1.i64(<vscale x 4 x i1> [[VALUE:%.*]], <vscale x 4 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
-void test_vse1_v_b16(uint8_t *base, vbool16_t value, size_t vl) {
- return vse1_v_b16(base, value, vl);
+void test_vsm_v_b16(uint8_t *base, vbool16_t value, size_t vl) {
+ return vsm_v_b16(base, value, vl);
}
-// CHECK-RV64-LABEL: @test_vse1_v_b32(
+// CHECK-RV64-LABEL: @test_vsm_v_b32(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i1>*
-// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv2i1.i64(<vscale x 2 x i1> [[VALUE:%.*]], <vscale x 2 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv2i1.i64(<vscale x 2 x i1> [[VALUE:%.*]], <vscale x 2 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
-void test_vse1_v_b32(uint8_t *base, vbool32_t value, size_t vl) {
- return vse1_v_b32(base, value, vl);
+void test_vsm_v_b32(uint8_t *base, vbool32_t value, size_t vl) {
+ return vsm_v_b32(base, value, vl);
}
-// CHECK-RV64-LABEL: @test_vse1_v_b64(
+// CHECK-RV64-LABEL: @test_vsm_v_b64(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i1>*
-// CHECK-RV64-NEXT: call void @llvm.riscv.vse1.nxv1i1.i64(<vscale x 1 x i1> [[VALUE:%.*]], <vscale x 1 x i1>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT: call void @llvm.riscv.vsm.nxv1i1.i64(<vscale x 1 x i1> [[VALUE:%.*]], <vscale x 1 x i1>* [[TMP0]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret void
//
-void test_vse1_v_b64(uint8_t *base, vbool64_t value, size_t vl) {
- return vse1_v_b64(base, value, vl);
+void test_vsm_v_b64(uint8_t *base, vbool64_t value, size_t vl) {
+ return vsm_v_b64(base, value, vl);
}
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 639f26943bccf..bc69f7566e9b3 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -973,8 +973,8 @@ let TargetPrefix = "riscv" in {
defm vsoxei : RISCVIStore;
defm vsuxei : RISCVIStore;
- def int_riscv_vle1 : RISCVUSLoad;
- def int_riscv_vse1 : RISCVUSStore;
+ def int_riscv_vlm : RISCVUSLoad;
+ def int_riscv_vsm : RISCVUSStore;
defm vamoswap : RISCVAMO;
defm vamoadd : RISCVAMO;
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index f942821e6bd81..ddf17097554ac 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1113,7 +1113,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
ReplaceNode(Node, Load);
return;
}
- case Intrinsic::riscv_vle1:
+ case Intrinsic::riscv_vlm:
case Intrinsic::riscv_vle:
case Intrinsic::riscv_vle_mask:
case Intrinsic::riscv_vlse:
@@ -1303,7 +1303,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
ReplaceNode(Node, Store);
return;
}
- case Intrinsic::riscv_vse1:
+ case Intrinsic::riscv_vsm:
case Intrinsic::riscv_vse:
case Intrinsic::riscv_vse_mask:
case Intrinsic::riscv_vsse:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index d1e67172c5568..b3df212a3a9ef 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -858,10 +858,14 @@ def VLE32FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth32, "vle32ff.v">,
def VLE64FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth64, "vle64ff.v">,
VLFSched<64>;
-def VLE1_V : VUnitStrideLoadMask<"vle1.v">,
+def VLM_V : VUnitStrideLoadMask<"vlm.v">,
Sched<[WriteVLDM, ReadVLDX]>;
-def VSE1_V : VUnitStrideStoreMask<"vse1.v">,
+def VSM_V : VUnitStrideStoreMask<"vsm.v">,
Sched<[WriteVSTM, ReadVSTM, ReadVSTX]>;
+def : InstAlias<"vle1.v $vd, (${rs1})",
+ (VLM_V VR:$vd, GPR:$rs1), 0>;
+def : InstAlias<"vse1.v $vs3, (${rs1})",
+ (VSM_V VR:$vs3, GPR:$rs1), 0>;
def VSE8_V : VUnitStrideStore<SUMOPUnitStride, LSWidth8, "vse8.v">,
VSESched<8>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index cc55731926a4b..359d5c04ef818 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -3534,8 +3534,8 @@ def PseudoVSETIVLI : Pseudo<(outs GPR:$rd), (ins uimm5:$rs1, VTypeIOp:$vtypei),
defm PseudoVL : VPseudoUSLoad</*isFF=*/false>;
defm PseudoVS : VPseudoUSStore;
-defm PseudoVLE1 : VPseudoLoadMask;
-defm PseudoVSE1 : VPseudoStoreMask;
+defm PseudoVLM : VPseudoLoadMask;
+defm PseudoVSM : VPseudoStoreMask;
//===----------------------------------------------------------------------===//
// 7.5 Vector Strided Instructions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index f9ff269944570..9c61161c2dc32 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -89,8 +89,8 @@ multiclass VPatUSLoadStoreWholeVRSDNode<ValueType type,
multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m>
{
- defvar load_instr = !cast<Instruction>("PseudoVLE1_V_"#m.BX);
- defvar store_instr = !cast<Instruction>("PseudoVSE1_V_"#m.BX);
+ defvar load_instr = !cast<Instruction>("PseudoVLM_V_"#m.BX);
+ defvar store_instr = !cast<Instruction>("PseudoVSM_V_"#m.BX);
// Load
def : Pat<(m.Mask (load BaseAddr:$rs1)),
(load_instr BaseAddr:$rs1, m.AVL, m.Log2SEW)>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 2c3f49c54f42d..aabbce96261d3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -622,8 +622,8 @@ foreach vti = AllVectors in {
}
foreach mti = AllMasks in {
- defvar load_instr = !cast<Instruction>("PseudoVLE1_V_"#mti.BX);
- defvar store_instr = !cast<Instruction>("PseudoVSE1_V_"#mti.BX);
+ defvar load_instr = !cast<Instruction>("PseudoVLM_V_"#mti.BX);
+ defvar store_instr = !cast<Instruction>("PseudoVSM_V_"#mti.BX);
def : Pat<(mti.Mask (riscv_vle_vl BaseAddr:$rs1, VLOpFrag)),
(load_instr BaseAddr:$rs1, GPR:$vl, mti.Log2SEW)>;
def : Pat<(riscv_vse_vl (mti.Mask VR:$rs2), BaseAddr:$rs1,
diff --git a/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll b/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
index 96371d1c2de11..95bdb493a70a5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
@@ -49,7 +49,7 @@ define fastcc <vscale x 8 x i1> @ret_mask_nxv8i1(<vscale x 8 x i1>* %p) {
; CHECK-LABEL: ret_mask_nxv8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
+; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret
%v = load <vscale x 8 x i1>, <vscale x 8 x i1>* %p
ret <vscale x 8 x i1> %v
@@ -59,7 +59,7 @@ define fastcc <vscale x 32 x i1> @ret_mask_nxv32i1(<vscale x 32 x i1>* %p) {
; CHECK-LABEL: ret_mask_nxv32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
+; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret
%v = load <vscale x 32 x i1>, <vscale x 32 x i1>* %p
ret <vscale x 32 x i1> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll b/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
index b102552862ae8..48ebe9f8ecad9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
@@ -6,7 +6,7 @@ define <vscale x 1 x i8> @sextload_nxv1i1_nxv1i8(<vscale x 1 x i1>* %x) {
; CHECK-LABEL: sextload_nxv1i1_nxv1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
+; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
; CHECK-NEXT: ret
@@ -399,7 +399,7 @@ define void @truncstore_nxv1i8_nxv1i1(<vscale x 1 x i8> %x, <vscale x 1 x i1> *%
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
; CHECK-NEXT: vand.vi v25, v8, 1
; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%y = trunc <vscale x 1 x i8> %x to <vscale x 1 x i1>
store <vscale x 1 x i1> %y, <vscale x 1 x i1>* %z
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
index dcdd59871b455..dafb9a179436f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
@@ -54,7 +54,7 @@ define fastcc <8 x i1> @ret_mask_v8i1(<8 x i1>* %p) {
; CHECK-LABEL: ret_mask_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
+; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret
%v = load <8 x i1>, <8 x i1>* %p
ret <8 x i1> %v
@@ -65,7 +65,7 @@ define fastcc <32 x i1> @ret_mask_v32i1(<32 x i1>* %p) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
+; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret
%v = load <32 x i1>, <32 x i1>* %p
ret <32 x i1> %v
@@ -561,7 +561,7 @@ define fastcc <4 x i1> @vector_mask_arg_direct_stack(i32 %0, i32 %1, i32 %2, i32
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: addi a0, sp, 152
-; CHECK-NEXT: vle1.v v25, (a0)
+; CHECK-NEXT: vlm.v v25, (a0)
; CHECK-NEXT: vmxor.mm v0, v0, v25
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
index d21b3d0811f16..35ab9360b8f20 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
@@ -108,7 +108,7 @@ define <8 x i1> @ret_mask_v8i1(<8 x i1>* %p) {
; CHECK-LABEL: ret_mask_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
+; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret
%v = load <8 x i1>, <8 x i1>* %p
ret <8 x i1> %v
@@ -119,29 +119,29 @@ define <32 x i1> @ret_mask_v32i1(<32 x i1>* %p) {
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: addi a1, zero, 32
; LMULMAX8-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX8-NEXT: vle1.v v0, (a0)
+; LMULMAX8-NEXT: vlm.v v0, (a0)
; LMULMAX8-NEXT: ret
;
; LMULMAX4-LABEL: ret_mask_v32i1:
; LMULMAX4: # %bb.0:
; LMULMAX4-NEXT: addi a1, zero, 32
; LMULMAX4-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX4-NEXT: vle1.v v0, (a0)
+; LMULMAX4-NEXT: vlm.v v0, (a0)
; LMULMAX4-NEXT: ret
;
; LMULMAX2-LABEL: ret_mask_v32i1:
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a1, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle1.v v0, (a0)
+; LMULMAX2-NEXT: vlm.v v0, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: ret_mask_v32i1:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vle1.v v0, (a0)
+; LMULMAX1-NEXT: vlm.v v0, (a0)
; LMULMAX1-NEXT: addi a0, a0, 2
-; LMULMAX1-NEXT: vle1.v v8, (a0)
+; LMULMAX1-NEXT: vlm.v v8, (a0)
; LMULMAX1-NEXT: ret
%v = load <32 x i1>, <32 x i1>* %p
ret <32 x i1> %v
@@ -1419,7 +1419,7 @@ define <4 x i1> @vector_mask_arg_via_stack(i32 %0, i32 %1, i32 %2, i32 %3, i32 %
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
; CHECK-NEXT: addi a0, sp, 152
-; CHECK-NEXT: vle1.v v0, (a0)
+; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
ret <4 x i1> %10
@@ -1453,7 +1453,7 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {
; LMULMAX8-NEXT: addi a5, zero, 5
; LMULMAX8-NEXT: addi a6, zero, 6
; LMULMAX8-NEXT: addi a7, zero, 7
-; LMULMAX8-NEXT: vse1.v v25, (a0)
+; LMULMAX8-NEXT: vsm.v v25, (a0)
; LMULMAX8-NEXT: mv a0, zero
; LMULMAX8-NEXT: mv a1, zero
; LMULMAX8-NEXT: mv a2, zero
@@ -1491,7 +1491,7 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {
; LMULMAX4-NEXT: addi a5, zero, 5
; LMULMAX4-NEXT: addi a6, zero, 6
; LMULMAX4-NEXT: addi a7, zero, 7
-; LMULMAX4-NEXT: vse1.v v25, (a0)
+; LMULMAX4-NEXT: vsm.v v25, (a0)
; LMULMAX4-NEXT: mv a0, zero
; LMULMAX4-NEXT: mv a1, zero
; LMULMAX4-NEXT: mv a2, zero
@@ -1535,7 +1535,7 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {
; LMULMAX2-NEXT: addi a5, zero, 5
; LMULMAX2-NEXT: addi a6, zero, 6
; LMULMAX2-NEXT: addi a7, zero, 7
-; LMULMAX2-NEXT: vse1.v v25, (a0)
+; LMULMAX2-NEXT: vsm.v v25, (a0)
; LMULMAX2-NEXT: mv a0, zero
; LMULMAX2-NEXT: mv a1, zero
; LMULMAX2-NEXT: mv a2, zero
@@ -1591,7 +1591,7 @@ define <4 x i1> @pass_vector_mask_arg_via_stack(<4 x i1> %v) {
; LMULMAX1-NEXT: addi a5, zero, 5
; LMULMAX1-NEXT: addi a6, zero, 6
; LMULMAX1-NEXT: addi a7, zero, 7
-; LMULMAX1-NEXT: vse1.v v25, (a0)
+; LMULMAX1-NEXT: vsm.v v25, (a0)
; LMULMAX1-NEXT: mv a0, zero
; LMULMAX1-NEXT: mv a1, zero
; LMULMAX1-NEXT: mv a2, zero
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
index ecfb70928fe6e..f332e0bc94191 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
@@ -8,7 +8,7 @@ define <2 x i16> @sextload_v2i1_v2i16(<2 x i1>* %x) {
; CHECK-LABEL: sextload_v2i1_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
+; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v8, v25, -1, v0
@@ -562,7 +562,7 @@ define void @truncstore_v2i8_v2i1(<2 x i8> %x, <2 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%y = trunc <2 x i8> %x to <2 x i1>
store <2 x i1> %y, <2 x i1>* %z
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
index 72843d45803c2..9b0741afe2edb 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
@@ -214,17 +214,17 @@ define void @extract_v8i1_v64i1_0(<64 x i1>* %x, <8 x i1>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle1.v v25, (a0)
+; LMULMAX2-NEXT: vlm.v v25, (a0)
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vse1.v v25, (a1)
+; LMULMAX2-NEXT: vsm.v v25, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v8i1_v64i1_0:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vle1.v v25, (a0)
+; LMULMAX1-NEXT: vlm.v v25, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vse1.v v25, (a1)
+; LMULMAX1-NEXT: vsm.v v25, (a1)
; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 0)
@@ -237,21 +237,21 @@ define void @extract_v8i1_v64i1_8(<64 x i1>* %x, <8 x i1>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle1.v v25, (a0)
+; LMULMAX2-NEXT: vlm.v v25, (a0)
; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; LMULMAX2-NEXT: vslidedown.vi v25, v25, 1
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vse1.v v25, (a1)
+; LMULMAX2-NEXT: vsm.v v25, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v8i1_v64i1_8:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vle1.v v25, (a0)
+; LMULMAX1-NEXT: vlm.v v25, (a0)
; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
; LMULMAX1-NEXT: vslidedown.vi v25, v25, 1
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vse1.v v25, (a1)
+; LMULMAX1-NEXT: vsm.v v25, (a1)
; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 8)
@@ -265,20 +265,20 @@ define void @extract_v8i1_v64i1_48(<64 x i1>* %x, <8 x i1>* %y) {
; LMULMAX2-NEXT: addi a0, a0, 4
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle1.v v25, (a0)
+; LMULMAX2-NEXT: vlm.v v25, (a0)
; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf4, ta, mu
; LMULMAX2-NEXT: vslidedown.vi v25, v25, 2
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vse1.v v25, (a1)
+; LMULMAX2-NEXT: vsm.v v25, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v8i1_v64i1_48:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a0, a0, 6
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vle1.v v25, (a0)
+; LMULMAX1-NEXT: vlm.v v25, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vse1.v v25, (a1)
+; LMULMAX1-NEXT: vsm.v v25, (a1)
; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.v64i1(<64 x i1> %a, i64 48)
@@ -290,7 +290,7 @@ define void @extract_v8i1_nxv2i1_0(<vscale x 2 x i1> %x, <8 x i1>* %y) {
; CHECK-LABEL: extract_v8i1_nxv2i1_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
+; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv2i1(<vscale x 2 x i1> %x, i64 0)
store <8 x i1> %c, <8 x i1>* %y
@@ -301,7 +301,7 @@ define void @extract_v8i1_nxv64i1_0(<vscale x 64 x i1> %x, <8 x i1>* %y) {
; CHECK-LABEL: extract_v8i1_nxv64i1_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
+; CHECK-NEXT: vsm.v v0, (a0)
; CHECK-NEXT: ret
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 0)
store <8 x i1> %c, <8 x i1>* %y
@@ -314,7 +314,7 @@ define void @extract_v8i1_nxv64i1_8(<vscale x 64 x i1> %x, <8 x i1>* %y) {
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v25, v0, 1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 8)
store <8 x i1> %c, <8 x i1>* %y
@@ -327,7 +327,7 @@ define void @extract_v8i1_nxv64i1_48(<vscale x 64 x i1> %x, <8 x i1>* %y) {
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, mu
; CHECK-NEXT: vslidedown.vi v25, v0, 6
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv64i1(<vscale x 64 x i1> %x, i64 48)
store <8 x i1> %c, <8 x i1>* %y
@@ -340,7 +340,7 @@ define void @extract_v2i1_v64i1_0(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle1.v v0, (a0)
+; LMULMAX2-NEXT: vlm.v v0, (a0)
; LMULMAX2-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; LMULMAX2-NEXT: vmv.v.i v25, 0
; LMULMAX2-NEXT: vmerge.vim v25, v25, 1, v0
@@ -350,13 +350,13 @@ define void @extract_v2i1_v64i1_0(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX2-NEXT: vslideup.vi v26, v25, 0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX2-NEXT: vmsne.vi v25, v26, 0
-; LMULMAX2-NEXT: vse1.v v25, (a1)
+; LMULMAX2-NEXT: vsm.v v25, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v2i1_v64i1_0:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vle1.v v0, (a0)
+; LMULMAX1-NEXT: vlm.v v0, (a0)
; LMULMAX1-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
@@ -366,7 +366,7 @@ define void @extract_v2i1_v64i1_0(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v25, v26, 0
-; LMULMAX1-NEXT: vse1.v v25, (a1)
+; LMULMAX1-NEXT: vsm.v v25, (a1)
; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 0)
@@ -379,7 +379,7 @@ define void @extract_v2i1_v64i1_2(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle1.v v0, (a0)
+; LMULMAX2-NEXT: vlm.v v0, (a0)
; LMULMAX2-NEXT: vmv.v.i v26, 0
; LMULMAX2-NEXT: vmerge.vim v26, v26, 1, v0
; LMULMAX2-NEXT: vsetivli zero, 2, e8, m2, ta, mu
@@ -394,13 +394,13 @@ define void @extract_v2i1_v64i1_2(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX2-NEXT: vslideup.vi v26, v25, 0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX2-NEXT: vmsne.vi v25, v26, 0
-; LMULMAX2-NEXT: vse1.v v25, (a1)
+; LMULMAX2-NEXT: vsm.v v25, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v2i1_v64i1_2:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vle1.v v0, (a0)
+; LMULMAX1-NEXT: vlm.v v0, (a0)
; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, m1, ta, mu
@@ -415,7 +415,7 @@ define void @extract_v2i1_v64i1_2(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v25, v26, 0
-; LMULMAX1-NEXT: vse1.v v25, (a1)
+; LMULMAX1-NEXT: vsm.v v25, (a1)
; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 2)
@@ -429,7 +429,7 @@ define void @extract_v2i1_v64i1_42(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX2-NEXT: addi a0, a0, 4
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle1.v v0, (a0)
+; LMULMAX2-NEXT: vlm.v v0, (a0)
; LMULMAX2-NEXT: vmv.v.i v26, 0
; LMULMAX2-NEXT: vmerge.vim v26, v26, 1, v0
; LMULMAX2-NEXT: vsetivli zero, 2, e8, m2, ta, mu
@@ -444,14 +444,14 @@ define void @extract_v2i1_v64i1_42(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX2-NEXT: vslideup.vi v26, v25, 0
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX2-NEXT: vmsne.vi v25, v26, 0
-; LMULMAX2-NEXT: vse1.v v25, (a1)
+; LMULMAX2-NEXT: vsm.v v25, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: extract_v2i1_v64i1_42:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a0, a0, 4
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vle1.v v0, (a0)
+; LMULMAX1-NEXT: vlm.v v0, (a0)
; LMULMAX1-NEXT: vmv.v.i v25, 0
; LMULMAX1-NEXT: vmerge.vim v25, v25, 1, v0
; LMULMAX1-NEXT: vsetivli zero, 2, e8, m1, ta, mu
@@ -466,7 +466,7 @@ define void @extract_v2i1_v64i1_42(<64 x i1>* %x, <2 x i1>* %y) {
; LMULMAX1-NEXT: vslideup.vi v26, v25, 0
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; LMULMAX1-NEXT: vmsne.vi v25, v26, 0
-; LMULMAX1-NEXT: vse1.v v25, (a1)
+; LMULMAX1-NEXT: vsm.v v25, (a1)
; LMULMAX1-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.v64i1(<64 x i1> %a, i64 42)
@@ -486,7 +486,7 @@ define void @extract_v2i1_nxv2i1_0(<vscale x 2 x i1> %x, <2 x i1>* %y) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 0)
store <2 x i1> %c, <2 x i1>* %y
@@ -511,7 +511,7 @@ define void @extract_v2i1_nxv2i1_2(<vscale x 2 x i1> %x, <2 x i1>* %y) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv2i1(<vscale x 2 x i1> %x, i64 2)
store <2 x i1> %c, <2 x i1>* %y
@@ -530,7 +530,7 @@ define void @extract_v2i1_nxv64i1_0(<vscale x 64 x i1> %x, <2 x i1>* %y) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 0)
store <2 x i1> %c, <2 x i1>* %y
@@ -555,7 +555,7 @@ define void @extract_v2i1_nxv64i1_2(<vscale x 64 x i1> %x, <2 x i1>* %y) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 2)
store <2 x i1> %c, <2 x i1>* %y
@@ -581,7 +581,7 @@ define void @extract_v2i1_nxv64i1_42(<vscale x 64 x i1> %x, <2 x i1>* %y) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv64i1(<vscale x 64 x i1> %x, i64 42)
store <2 x i1> %c, <2 x i1>* %y
@@ -606,7 +606,7 @@ define void @extract_v2i1_nxv32i1_26(<vscale x 32 x i1> %x, <2 x i1>* %y) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%c = call <2 x i1> @llvm.experimental.vector.extract.v2i1.nxv32i1(<vscale x 32 x i1> %x, i64 26)
store <2 x i1> %c, <2 x i1>* %y
@@ -619,7 +619,7 @@ define void @extract_v8i1_nxv32i1_16(<vscale x 32 x i1> %x, <8 x i1>* %y) {
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, mu
; CHECK-NEXT: vslidedown.vi v25, v0, 2
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%c = call <8 x i1> @llvm.experimental.vector.extract.v8i1.nxv32i1(<vscale x 32 x i1> %x, i64 16)
store <8 x i1> %c, <8 x i1>* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
index 0cc6670365908..60508396aec1e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
@@ -9,7 +9,7 @@ define void @fcmp_oeq_vv_v8f16(<8 x half>* %x, <8 x half>* %y, <8 x i1>* %z) {
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vle16.v v26, (a1)
; CHECK-NEXT: vmfeq.vv v25, v25, v26
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = load <8 x half>, <8 x half>* %y
@@ -25,7 +25,7 @@ define void @fcmp_oeq_vv_v8f16_nonans(<8 x half>* %x, <8 x half>* %y, <8 x i1>*
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vle16.v v26, (a1)
; CHECK-NEXT: vmfeq.vv v25, v25, v26
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = load <8 x half>, <8 x half>* %y
@@ -50,7 +50,7 @@ define void @fcmp_une_vv_v4f32(<4 x float>* %x, <4 x float>* %y, <4 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -75,7 +75,7 @@ define void @fcmp_une_vv_v4f32_nonans(<4 x float>* %x, <4 x float>* %y, <4 x i1>
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = load <4 x float>, <4 x float>* %y
@@ -100,7 +100,7 @@ define void @fcmp_ogt_vv_v2f64(<2 x double>* %x, <2 x double>* %y, <2 x i1>* %z)
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -125,7 +125,7 @@ define void @fcmp_ogt_vv_v2f64_nonans(<2 x double>* %x, <2 x double>* %y, <2 x i
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = load <2 x double>, <2 x double>* %y
@@ -141,7 +141,7 @@ define void @fcmp_olt_vv_v16f16(<16 x half>* %x, <16 x half>* %y, <16 x i1>* %z)
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: vle16.v v28, (a1)
; CHECK-NEXT: vmflt.vv v25, v26, v28
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = load <16 x half>, <16 x half>* %y
@@ -157,7 +157,7 @@ define void @fcmp_olt_vv_v16f16_nonans(<16 x half>* %x, <16 x half>* %y, <16 x i
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: vle16.v v28, (a1)
; CHECK-NEXT: vmflt.vv v25, v26, v28
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = load <16 x half>, <16 x half>* %y
@@ -173,7 +173,7 @@ define void @fcmp_oge_vv_v8f32(<8 x float>* %x, <8 x float>* %y, <8 x i1>* %z) {
; CHECK-NEXT: vle32.v v26, (a0)
; CHECK-NEXT: vle32.v v28, (a1)
; CHECK-NEXT: vmfle.vv v25, v28, v26
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = load <8 x float>, <8 x float>* %y
@@ -189,7 +189,7 @@ define void @fcmp_oge_vv_v8f32_nonans(<8 x float>* %x, <8 x float>* %y, <8 x i1>
; CHECK-NEXT: vle32.v v26, (a0)
; CHECK-NEXT: vle32.v v28, (a1)
; CHECK-NEXT: vmfle.vv v25, v28, v26
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = load <8 x float>, <8 x float>* %y
@@ -214,7 +214,7 @@ define void @fcmp_ole_vv_v4f64(<4 x double>* %x, <4 x double>* %y, <4 x i1>* %z)
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = load <4 x double>, <4 x double>* %y
@@ -239,7 +239,7 @@ define void @fcmp_ole_vv_v4f64_nonans(<4 x double>* %x, <4 x double>* %y, <4 x i
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = load <4 x double>, <4 x double>* %y
@@ -257,7 +257,7 @@ define void @fcmp_ule_vv_v32f16(<32 x half>* %x, <32 x half>* %y, <32 x i1>* %z)
; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: vmflt.vv v25, v8, v28
; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <32 x half>, <32 x half>* %x
%b = load <32 x half>, <32 x half>* %y
@@ -274,7 +274,7 @@ define void @fcmp_ule_vv_v32f16_nonans(<32 x half>* %x, <32 x half>* %y, <32 x i
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: vmfle.vv v25, v28, v8
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <32 x half>, <32 x half>* %x
%b = load <32 x half>, <32 x half>* %y
@@ -291,7 +291,7 @@ define void @fcmp_uge_vv_v16f32(<16 x float>* %x, <16 x float>* %y, <16 x i1>* %
; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vmflt.vv v25, v28, v8
; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x
%b = load <16 x float>, <16 x float>* %y
@@ -307,7 +307,7 @@ define void @fcmp_uge_vv_v16f32_nonans(<16 x float>* %x, <16 x float>* %y, <16 x
; CHECK-NEXT: vle32.v v28, (a0)
; CHECK-NEXT: vle32.v v8, (a1)
; CHECK-NEXT: vmfle.vv v25, v8, v28
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x
%b = load <16 x float>, <16 x float>* %y
@@ -324,7 +324,7 @@ define void @fcmp_ult_vv_v8f64(<8 x double>* %x, <8 x double>* %y, <8 x i1>* %z)
; CHECK-NEXT: vle64.v v8, (a1)
; CHECK-NEXT: vmfle.vv v25, v8, v28
; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%b = load <8 x double>, <8 x double>* %y
@@ -340,7 +340,7 @@ define void @fcmp_ult_vv_v8f64_nonans(<8 x double>* %x, <8 x double>* %y, <8 x i
; CHECK-NEXT: vle64.v v28, (a0)
; CHECK-NEXT: vle64.v v8, (a1)
; CHECK-NEXT: vmflt.vv v25, v28, v8
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%b = load <8 x double>, <8 x double>* %y
@@ -358,7 +358,7 @@ define void @fcmp_ugt_vv_v64f16(<64 x half>* %x, <64 x half>* %y, <64 x i1>* %z)
; CHECK-NEXT: vle16.v v16, (a1)
; CHECK-NEXT: vmfle.vv v25, v8, v16
; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <64 x half>, <64 x half>* %x
%b = load <64 x half>, <64 x half>* %y
@@ -375,7 +375,7 @@ define void @fcmp_ugt_vv_v64f16_nonans(<64 x half>* %x, <64 x half>* %y, <64 x i
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vle16.v v16, (a1)
; CHECK-NEXT: vmflt.vv v25, v16, v8
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <64 x half>, <64 x half>* %x
%b = load <64 x half>, <64 x half>* %y
@@ -394,7 +394,7 @@ define void @fcmp_ueq_vv_v32f32(<32 x float>* %x, <32 x float>* %y, <32 x i1>* %
; CHECK-NEXT: vmflt.vv v25, v8, v16
; CHECK-NEXT: vmflt.vv v26, v16, v8
; CHECK-NEXT: vmnor.mm v25, v26, v25
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = load <32 x float>, <32 x float>* %y
@@ -411,7 +411,7 @@ define void @fcmp_ueq_vv_v32f32_nonans(<32 x float>* %x, <32 x float>* %y, <32 x
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vle32.v v16, (a1)
; CHECK-NEXT: vmfeq.vv v25, v8, v16
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = load <32 x float>, <32 x float>* %y
@@ -429,7 +429,7 @@ define void @fcmp_one_vv_v8f64(<16 x double>* %x, <16 x double>* %y, <16 x i1>*
; CHECK-NEXT: vmflt.vv v25, v8, v16
; CHECK-NEXT: vmflt.vv v26, v16, v8
; CHECK-NEXT: vmor.mm v25, v26, v25
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = load <16 x double>, <16 x double>* %y
@@ -445,7 +445,7 @@ define void @fcmp_one_vv_v8f64_nonans(<16 x double>* %x, <16 x double>* %y, <16
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: vmfne.vv v25, v8, v16
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = load <16 x double>, <16 x double>* %y
@@ -472,7 +472,7 @@ define void @fcmp_ord_vv_v4f16(<4 x half>* %x, <4 x half>* %y, <4 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <4 x half>, <4 x half>* %x
%b = load <4 x half>, <4 x half>* %y
@@ -499,7 +499,7 @@ define void @fcmp_uno_vv_v4f16(<2 x half>* %x, <2 x half>* %y, <2 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x
%b = load <2 x half>, <2 x half>* %y
@@ -514,7 +514,7 @@ define void @fcmp_oeq_vf_v8f16(<8 x half>* %x, half %y, <8 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vmfeq.vf v25, v25, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -530,7 +530,7 @@ define void @fcmp_oeq_vf_v8f16_nonans(<8 x half>* %x, half %y, <8 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vmfeq.vf v25, v25, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -555,7 +555,7 @@ define void @fcmp_une_vf_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -580,7 +580,7 @@ define void @fcmp_une_vf_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -605,7 +605,7 @@ define void @fcmp_ogt_vf_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -630,7 +630,7 @@ define void @fcmp_ogt_vf_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z)
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -646,7 +646,7 @@ define void @fcmp_olt_vf_v16f16(<16 x half>* %x, half %y, <16 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: vmflt.vf v25, v26, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = insertelement <16 x half> undef, half %y, i32 0
@@ -662,7 +662,7 @@ define void @fcmp_olt_vf_v16f16_nonans(<16 x half>* %x, half %y, <16 x i1>* %z)
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: vmflt.vf v25, v26, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = insertelement <16 x half> undef, half %y, i32 0
@@ -678,7 +678,7 @@ define void @fcmp_oge_vf_v8f32(<8 x float>* %x, float %y, <8 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v26, (a0)
; CHECK-NEXT: vmfge.vf v25, v26, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = insertelement <8 x float> undef, float %y, i32 0
@@ -694,7 +694,7 @@ define void @fcmp_oge_vf_v8f32_nonans(<8 x float>* %x, float %y, <8 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v26, (a0)
; CHECK-NEXT: vmfge.vf v25, v26, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = insertelement <8 x float> undef, float %y, i32 0
@@ -719,7 +719,7 @@ define void @fcmp_ole_vf_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> undef, double %y, i32 0
@@ -744,7 +744,7 @@ define void @fcmp_ole_vf_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z)
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> undef, double %y, i32 0
@@ -762,7 +762,7 @@ define void @fcmp_ule_vf_v32f16(<32 x half>* %x, half %y, <32 x i1>* %z) {
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vmfgt.vf v25, v28, fa0
; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <32 x half>, <32 x half>* %x
%b = insertelement <32 x half> undef, half %y, i32 0
@@ -779,7 +779,7 @@ define void @fcmp_ule_vf_v32f16_nonans(<32 x half>* %x, half %y, <32 x i1>* %z)
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vmfle.vf v25, v28, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <32 x half>, <32 x half>* %x
%b = insertelement <32 x half> undef, half %y, i32 0
@@ -796,7 +796,7 @@ define void @fcmp_uge_vf_v16f32(<16 x float>* %x, float %y, <16 x i1>* %z) {
; CHECK-NEXT: vle32.v v28, (a0)
; CHECK-NEXT: vmflt.vf v25, v28, fa0
; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x
%b = insertelement <16 x float> undef, float %y, i32 0
@@ -812,7 +812,7 @@ define void @fcmp_uge_vf_v16f32_nonans(<16 x float>* %x, float %y, <16 x i1>* %z
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v28, (a0)
; CHECK-NEXT: vmfge.vf v25, v28, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x
%b = insertelement <16 x float> undef, float %y, i32 0
@@ -829,7 +829,7 @@ define void @fcmp_ult_vf_v8f64(<8 x double>* %x, double %y, <8 x i1>* %z) {
; CHECK-NEXT: vle64.v v28, (a0)
; CHECK-NEXT: vmfge.vf v25, v28, fa0
; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%b = insertelement <8 x double> undef, double %y, i32 0
@@ -845,7 +845,7 @@ define void @fcmp_ult_vf_v8f64_nonans(<8 x double>* %x, double %y, <8 x i1>* %z)
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; CHECK-NEXT: vle64.v v28, (a0)
; CHECK-NEXT: vmflt.vf v25, v28, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%b = insertelement <8 x double> undef, double %y, i32 0
@@ -863,7 +863,7 @@ define void @fcmp_ugt_vf_v64f16(<64 x half>* %x, half %y, <64 x i1>* %z) {
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmfle.vf v25, v8, fa0
; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <64 x half>, <64 x half>* %x
%b = insertelement <64 x half> undef, half %y, i32 0
@@ -880,7 +880,7 @@ define void @fcmp_ugt_vf_v64f16_nonans(<64 x half>* %x, half %y, <64 x i1>* %z)
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmfgt.vf v25, v8, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <64 x half>, <64 x half>* %x
%b = insertelement <64 x half> undef, half %y, i32 0
@@ -899,7 +899,7 @@ define void @fcmp_ueq_vf_v32f32(<32 x float>* %x, float %y, <32 x i1>* %z) {
; CHECK-NEXT: vmflt.vf v25, v8, fa0
; CHECK-NEXT: vmfgt.vf v26, v8, fa0
; CHECK-NEXT: vmnor.mm v25, v26, v25
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = insertelement <32 x float> undef, float %y, i32 0
@@ -916,7 +916,7 @@ define void @fcmp_ueq_vf_v32f32_nonans(<32 x float>* %x, float %y, <32 x i1>* %z
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfeq.vf v25, v8, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = insertelement <32 x float> undef, float %y, i32 0
@@ -934,7 +934,7 @@ define void @fcmp_one_vf_v8f64(<16 x double>* %x, double %y, <16 x i1>* %z) {
; CHECK-NEXT: vmflt.vf v25, v8, fa0
; CHECK-NEXT: vmfgt.vf v26, v8, fa0
; CHECK-NEXT: vmor.mm v25, v26, v25
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = insertelement <16 x double> undef, double %y, i32 0
@@ -950,7 +950,7 @@ define void @fcmp_one_vf_v8f64_nonans(<16 x double>* %x, double %y, <16 x i1>* %
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vf v25, v8, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = insertelement <16 x double> undef, double %y, i32 0
@@ -978,7 +978,7 @@ define void @fcmp_ord_vf_v4f16(<4 x half>* %x, half %y, <4 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <4 x half>, <4 x half>* %x
%b = insertelement <4 x half> undef, half %y, i32 0
@@ -1006,7 +1006,7 @@ define void @fcmp_uno_vf_v4f16(<2 x half>* %x, half %y, <2 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x
%b = insertelement <2 x half> undef, half %y, i32 0
@@ -1022,7 +1022,7 @@ define void @fcmp_oeq_fv_v8f16(<8 x half>* %x, half %y, <8 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vmfeq.vf v25, v25, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -1038,7 +1038,7 @@ define void @fcmp_oeq_fv_v8f16_nonans(<8 x half>* %x, half %y, <8 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vmfeq.vf v25, v25, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x
%b = insertelement <8 x half> undef, half %y, i32 0
@@ -1063,7 +1063,7 @@ define void @fcmp_une_fv_v4f32(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -1088,7 +1088,7 @@ define void @fcmp_une_fv_v4f32_nonans(<4 x float>* %x, float %y, <4 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x
%b = insertelement <4 x float> undef, float %y, i32 0
@@ -1113,7 +1113,7 @@ define void @fcmp_ogt_fv_v2f64(<2 x double>* %x, double %y, <2 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -1138,7 +1138,7 @@ define void @fcmp_ogt_fv_v2f64_nonans(<2 x double>* %x, double %y, <2 x i1>* %z)
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x
%b = insertelement <2 x double> undef, double %y, i32 0
@@ -1154,7 +1154,7 @@ define void @fcmp_olt_fv_v16f16(<16 x half>* %x, half %y, <16 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: vmfgt.vf v25, v26, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = insertelement <16 x half> undef, half %y, i32 0
@@ -1170,7 +1170,7 @@ define void @fcmp_olt_fv_v16f16_nonans(<16 x half>* %x, half %y, <16 x i1>* %z)
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: vmfgt.vf v25, v26, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <16 x half>, <16 x half>* %x
%b = insertelement <16 x half> undef, half %y, i32 0
@@ -1186,7 +1186,7 @@ define void @fcmp_oge_fv_v8f32(<8 x float>* %x, float %y, <8 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v26, (a0)
; CHECK-NEXT: vmfle.vf v25, v26, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = insertelement <8 x float> undef, float %y, i32 0
@@ -1202,7 +1202,7 @@ define void @fcmp_oge_fv_v8f32_nonans(<8 x float>* %x, float %y, <8 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v26, (a0)
; CHECK-NEXT: vmfle.vf v25, v26, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <8 x float>, <8 x float>* %x
%b = insertelement <8 x float> undef, float %y, i32 0
@@ -1227,7 +1227,7 @@ define void @fcmp_ole_fv_v4f64(<4 x double>* %x, double %y, <4 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> undef, double %y, i32 0
@@ -1252,7 +1252,7 @@ define void @fcmp_ole_fv_v4f64_nonans(<4 x double>* %x, double %y, <4 x i1>* %z)
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <4 x double>, <4 x double>* %x
%b = insertelement <4 x double> undef, double %y, i32 0
@@ -1270,7 +1270,7 @@ define void @fcmp_ule_fv_v32f16(<32 x half>* %x, half %y, <32 x i1>* %z) {
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vmflt.vf v25, v28, fa0
; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <32 x half>, <32 x half>* %x
%b = insertelement <32 x half> undef, half %y, i32 0
@@ -1287,7 +1287,7 @@ define void @fcmp_ule_fv_v32f16_nonans(<32 x half>* %x, half %y, <32 x i1>* %z)
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vmfge.vf v25, v28, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <32 x half>, <32 x half>* %x
%b = insertelement <32 x half> undef, half %y, i32 0
@@ -1304,7 +1304,7 @@ define void @fcmp_uge_fv_v16f32(<16 x float>* %x, float %y, <16 x i1>* %z) {
; CHECK-NEXT: vle32.v v28, (a0)
; CHECK-NEXT: vmfgt.vf v25, v28, fa0
; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x
%b = insertelement <16 x float> undef, float %y, i32 0
@@ -1320,7 +1320,7 @@ define void @fcmp_uge_fv_v16f32_nonans(<16 x float>* %x, float %y, <16 x i1>* %z
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vle32.v v28, (a0)
; CHECK-NEXT: vmfle.vf v25, v28, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <16 x float>, <16 x float>* %x
%b = insertelement <16 x float> undef, float %y, i32 0
@@ -1337,7 +1337,7 @@ define void @fcmp_ult_fv_v8f64(<8 x double>* %x, double %y, <8 x i1>* %z) {
; CHECK-NEXT: vle64.v v28, (a0)
; CHECK-NEXT: vmfle.vf v25, v28, fa0
; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%b = insertelement <8 x double> undef, double %y, i32 0
@@ -1353,7 +1353,7 @@ define void @fcmp_ult_fv_v8f64_nonans(<8 x double>* %x, double %y, <8 x i1>* %z)
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; CHECK-NEXT: vle64.v v28, (a0)
; CHECK-NEXT: vmfgt.vf v25, v28, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <8 x double>, <8 x double>* %x
%b = insertelement <8 x double> undef, double %y, i32 0
@@ -1371,7 +1371,7 @@ define void @fcmp_ugt_fv_v64f16(<64 x half>* %x, half %y, <64 x i1>* %z) {
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmfge.vf v25, v8, fa0
; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <64 x half>, <64 x half>* %x
%b = insertelement <64 x half> undef, half %y, i32 0
@@ -1388,7 +1388,7 @@ define void @fcmp_ugt_fv_v64f16_nonans(<64 x half>* %x, half %y, <64 x i1>* %z)
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, mu
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmflt.vf v25, v8, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <64 x half>, <64 x half>* %x
%b = insertelement <64 x half> undef, half %y, i32 0
@@ -1407,7 +1407,7 @@ define void @fcmp_ueq_fv_v32f32(<32 x float>* %x, float %y, <32 x i1>* %z) {
; CHECK-NEXT: vmfgt.vf v25, v8, fa0
; CHECK-NEXT: vmflt.vf v26, v8, fa0
; CHECK-NEXT: vmnor.mm v25, v26, v25
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = insertelement <32 x float> undef, float %y, i32 0
@@ -1424,7 +1424,7 @@ define void @fcmp_ueq_fv_v32f32_nonans(<32 x float>* %x, float %y, <32 x i1>* %z
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, mu
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vmfeq.vf v25, v8, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <32 x float>, <32 x float>* %x
%b = insertelement <32 x float> undef, float %y, i32 0
@@ -1442,7 +1442,7 @@ define void @fcmp_one_fv_v8f64(<16 x double>* %x, double %y, <16 x i1>* %z) {
; CHECK-NEXT: vmfgt.vf v25, v8, fa0
; CHECK-NEXT: vmflt.vf v26, v8, fa0
; CHECK-NEXT: vmor.mm v25, v26, v25
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = insertelement <16 x double> undef, double %y, i32 0
@@ -1458,7 +1458,7 @@ define void @fcmp_one_fv_v8f64_nonans(<16 x double>* %x, double %y, <16 x i1>* %
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vf v25, v8, fa0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <16 x double>, <16 x double>* %x
%b = insertelement <16 x double> undef, double %y, i32 0
@@ -1486,7 +1486,7 @@ define void @fcmp_ord_fv_v4f16(<4 x half>* %x, half %y, <4 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <4 x half>, <4 x half>* %x
%b = insertelement <4 x half> undef, half %y, i32 0
@@ -1514,7 +1514,7 @@ define void @fcmp_uno_fv_v4f16(<2 x half>* %x, half %y, <2 x i1>* %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <2 x half>, <2 x half>* %x
%b = insertelement <2 x half> undef, half %y, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
index efb37c388e73c..14f8d2667d278 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
@@ -317,25 +317,25 @@ define void @insert_v32i1_v8i1_0(<32 x i1>* %vp, <8 x i1>* %svp) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle1.v v25, (a0)
+; LMULMAX2-NEXT: vlm.v v25, (a0)
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vle1.v v26, (a1)
+; LMULMAX2-NEXT: vlm.v v26, (a1)
; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf4, tu, mu
; LMULMAX2-NEXT: vslideup.vi v25, v26, 0
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vse1.v v25, (a0)
+; LMULMAX2-NEXT: vsm.v v25, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: insert_v32i1_v8i1_0:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vle1.v v25, (a0)
+; LMULMAX1-NEXT: vlm.v v25, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vle1.v v26, (a1)
+; LMULMAX1-NEXT: vlm.v v26, (a1)
; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, tu, mu
; LMULMAX1-NEXT: vslideup.vi v25, v26, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vse1.v v25, (a0)
+; LMULMAX1-NEXT: vsm.v v25, (a0)
; LMULMAX1-NEXT: ret
%v = load <32 x i1>, <32 x i1>* %vp
%sv = load <8 x i1>, <8 x i1>* %svp
@@ -349,26 +349,26 @@ define void @insert_v32i1_v8i1_16(<32 x i1>* %vp, <8 x i1>* %svp) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle1.v v25, (a0)
+; LMULMAX2-NEXT: vlm.v v25, (a0)
; LMULMAX2-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX2-NEXT: vle1.v v26, (a1)
+; LMULMAX2-NEXT: vlm.v v26, (a1)
; LMULMAX2-NEXT: vsetivli zero, 3, e8, mf4, tu, mu
; LMULMAX2-NEXT: vslideup.vi v25, v26, 2
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vse1.v v25, (a0)
+; LMULMAX2-NEXT: vsm.v v25, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-LABEL: insert_v32i1_v8i1_16:
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: addi a0, a0, 2
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vle1.v v25, (a0)
+; LMULMAX1-NEXT: vlm.v v25, (a0)
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; LMULMAX1-NEXT: vle1.v v26, (a1)
+; LMULMAX1-NEXT: vlm.v v26, (a1)
; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, tu, mu
; LMULMAX1-NEXT: vslideup.vi v25, v26, 0
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; LMULMAX1-NEXT: vse1.v v25, (a0)
+; LMULMAX1-NEXT: vsm.v v25, (a0)
; LMULMAX1-NEXT: ret
%v = load <32 x i1>, <32 x i1>* %vp
%sv = load <8 x i1>, <8 x i1>* %svp
@@ -381,9 +381,9 @@ define void @insert_v8i1_v4i1_0(<8 x i1>* %vp, <4 x i1>* %svp) {
; CHECK-LABEL: insert_v8i1_v4i1_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
+; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle1.v v25, (a1)
+; CHECK-NEXT: vlm.v v25, (a1)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
@@ -395,7 +395,7 @@ define void @insert_v8i1_v4i1_0(<8 x i1>* %vp, <4 x i1>* %svp) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%v = load <8 x i1>, <8 x i1>* %vp
%sv = load <4 x i1>, <4 x i1>* %svp
@@ -408,9 +408,9 @@ define void @insert_v8i1_v4i1_4(<8 x i1>* %vp, <4 x i1>* %svp) {
; CHECK-LABEL: insert_v8i1_v4i1_4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
+; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle1.v v25, (a1)
+; CHECK-NEXT: vlm.v v25, (a1)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
@@ -422,7 +422,7 @@ define void @insert_v8i1_v4i1_4(<8 x i1>* %vp, <4 x i1>* %svp) {
; CHECK-NEXT: vslideup.vi v26, v25, 4
; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%v = load <8 x i1>, <8 x i1>* %vp
%sv = load <4 x i1>, <4 x i1>* %svp
@@ -461,7 +461,7 @@ define <vscale x 2 x i1> @insert_nxv2i1_v4i1_0(<vscale x 2 x i1> %v, <4 x i1>* %
; CHECK-LABEL: insert_nxv2i1_v4i1_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
+; CHECK-NEXT: vlm.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vmerge.vim v26, v26, 1, v0
@@ -483,7 +483,7 @@ define <vscale x 8 x i1> @insert_nxv8i1_v4i1_0(<vscale x 8 x i1> %v, <8 x i1>* %
; CHECK-LABEL: insert_nxv8i1_v4i1_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
+; CHECK-NEXT: vlm.v v25, (a0)
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, tu, mu
; CHECK-NEXT: vslideup.vi v0, v25, 0
; CHECK-NEXT: ret
@@ -496,7 +496,7 @@ define <vscale x 8 x i1> @insert_nxv8i1_v8i1_16(<vscale x 8 x i1> %v, <8 x i1>*
; CHECK-LABEL: insert_nxv8i1_v8i1_16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
+; CHECK-NEXT: vlm.v v25, (a0)
; CHECK-NEXT: vsetivli zero, 3, e8, mf8, tu, mu
; CHECK-NEXT: vslideup.vi v0, v25, 2
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
index 96afc665ae631..6ad98d1b1f534 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
@@ -53,7 +53,7 @@ define void @setgt_vv_v64i8(<64 x i8>* %x, <64 x i8>* %y, <64 x i1>* %z) {
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vle8.v v8, (a1)
; CHECK-NEXT: vmslt.vv v25, v8, v28
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = load <64 x i8>, <64 x i8>* %y
@@ -70,7 +70,7 @@ define void @setlt_vv_v128i8(<128 x i8>* %x, <128 x i8>* %y, <128 x i1>* %z) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vle8.v v16, (a1)
; CHECK-NEXT: vmslt.vv v25, v8, v16
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = load <128 x i8>, <128 x i8>* %y
@@ -86,7 +86,7 @@ define void @setge_vv_v8i8(<8 x i8>* %x, <8 x i8>* %y, <8 x i1>* %z) {
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vle8.v v26, (a1)
; CHECK-NEXT: vmsle.vv v25, v26, v25
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load <8 x i8>, <8 x i8>* %y
@@ -102,7 +102,7 @@ define void @setle_vv_v16i8(<16 x i8>* %x, <16 x i8>* %y, <16 x i1>* %z) {
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vle8.v v26, (a1)
; CHECK-NEXT: vmsle.vv v25, v25, v26
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = load <16 x i8>, <16 x i8>* %y
@@ -119,7 +119,7 @@ define void @setugt_vv_v32i8(<32 x i8>* %x, <32 x i8>* %y, <32 x i1>* %z) {
; CHECK-NEXT: vle8.v v26, (a0)
; CHECK-NEXT: vle8.v v28, (a1)
; CHECK-NEXT: vmsltu.vv v25, v28, v26
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = load <32 x i8>, <32 x i8>* %y
@@ -136,7 +136,7 @@ define void @setult_vv_v64i8(<64 x i8>* %x, <64 x i8>* %y, <64 x i1>* %z) {
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vle8.v v8, (a1)
; CHECK-NEXT: vmsltu.vv v25, v28, v8
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = load <64 x i8>, <64 x i8>* %y
@@ -153,7 +153,7 @@ define void @setuge_vv_v128i8(<128 x i8>* %x, <128 x i8>* %y, <128 x i1>* %z) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vle8.v v16, (a1)
; CHECK-NEXT: vmsleu.vv v25, v16, v8
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = load <128 x i8>, <128 x i8>* %y
@@ -169,7 +169,7 @@ define void @setule_vv_v8i8(<8 x i8>* %x, <8 x i8>* %y, <8 x i1>* %z) {
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vle8.v v26, (a1)
; CHECK-NEXT: vmsleu.vv v25, v25, v26
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = load <8 x i8>, <8 x i8>* %y
@@ -184,7 +184,7 @@ define void @seteq_vx_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vmseq.vx v25, v25, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -201,7 +201,7 @@ define void @setne_vx_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v26, (a0)
; CHECK-NEXT: vmsne.vx v25, v26, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 %y, i32 0
@@ -218,7 +218,7 @@ define void @setgt_vx_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vmsgt.vx v25, v28, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 %y, i32 0
@@ -235,7 +235,7 @@ define void @setlt_vx_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmslt.vx v25, v8, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = insertelement <128 x i8> undef, i8 %y, i32 0
@@ -252,7 +252,7 @@ define void @setge_vx_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vmv.v.x v26, a1
; CHECK-NEXT: vmsle.vv v25, v26, v25
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 %y, i32 0
@@ -268,7 +268,7 @@ define void @setle_vx_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vmsle.vx v25, v25, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -285,7 +285,7 @@ define void @setugt_vx_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v26, (a0)
; CHECK-NEXT: vmsgtu.vx v25, v26, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 %y, i32 0
@@ -302,7 +302,7 @@ define void @setult_vx_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vmsltu.vx v25, v28, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 %y, i32 0
@@ -320,7 +320,7 @@ define void @setuge_vx_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.v.x v16, a1
; CHECK-NEXT: vmsleu.vv v25, v16, v8
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = insertelement <128 x i8> undef, i8 %y, i32 0
@@ -336,7 +336,7 @@ define void @setule_vx_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vmsleu.vx v25, v25, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 %y, i32 0
@@ -352,7 +352,7 @@ define void @seteq_xv_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vmseq.vx v25, v25, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -369,7 +369,7 @@ define void @setne_xv_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v26, (a0)
; CHECK-NEXT: vmsne.vx v25, v26, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 %y, i32 0
@@ -386,7 +386,7 @@ define void @setgt_xv_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vmslt.vx v25, v28, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 %y, i32 0
@@ -403,7 +403,7 @@ define void @setlt_xv_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmsgt.vx v25, v8, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = insertelement <128 x i8> undef, i8 %y, i32 0
@@ -419,7 +419,7 @@ define void @setge_xv_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vmsle.vx v25, v25, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 %y, i32 0
@@ -436,7 +436,7 @@ define void @setle_xv_v16i8(<16 x i8>* %x, i8 %y, <16 x i1>* %z) {
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vmv.v.x v26, a1
; CHECK-NEXT: vmsle.vv v25, v26, v25
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 %y, i32 0
@@ -453,7 +453,7 @@ define void @setugt_xv_v32i8(<32 x i8>* %x, i8 %y, <32 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a3, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v26, (a0)
; CHECK-NEXT: vmsltu.vx v25, v26, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 %y, i32 0
@@ -470,7 +470,7 @@ define void @setult_xv_v64i8(<64 x i8>* %x, i8 %y, <64 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a3, e8, m4, ta, mu
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vmsgtu.vx v25, v28, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 %y, i32 0
@@ -487,7 +487,7 @@ define void @setuge_xv_v128i8(<128 x i8>* %x, i8 %y, <128 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmsleu.vx v25, v8, a1
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = insertelement <128 x i8> undef, i8 %y, i32 0
@@ -504,7 +504,7 @@ define void @setule_xv_v8i8(<8 x i8>* %x, i8 %y, <8 x i1>* %z) {
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vmv.v.x v26, a1
; CHECK-NEXT: vmsleu.vv v25, v26, v25
-; CHECK-NEXT: vse1.v v25, (a2)
+; CHECK-NEXT: vsm.v v25, (a2)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 %y, i32 0
@@ -520,7 +520,7 @@ define void @seteq_vi_v16i8(<16 x i8>* %x, <16 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vmseq.vi v25, v25, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 0, i32 0
@@ -537,7 +537,7 @@ define void @setne_vi_v32i8(<32 x i8>* %x, <32 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; CHECK-NEXT: vle8.v v26, (a0)
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 0, i32 0
@@ -554,7 +554,7 @@ define void @setgt_vi_v64i8(<64 x i8>* %x, <64 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vmsgt.vx v25, v28, zero
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 0, i32 0
@@ -571,7 +571,7 @@ define void @setlt_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmsle.vi v25, v8, -1
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = insertelement <128 x i8> undef, i8 0, i32 0
@@ -587,7 +587,7 @@ define void @setge_vi_v8i8(<8 x i8>* %x, <8 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vmsgt.vi v25, v25, -1
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 0, i32 0
@@ -603,7 +603,7 @@ define void @setle_vi_v16i8(<16 x i8>* %x, <16 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vmsle.vi v25, v25, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <16 x i8>, <16 x i8>* %x
%b = insertelement <16 x i8> undef, i8 0, i32 0
@@ -621,7 +621,7 @@ define void @setugt_vi_v32i8(<32 x i8>* %x, <32 x i1>* %z) {
; CHECK-NEXT: vle8.v v26, (a0)
; CHECK-NEXT: addi a0, zero, 5
; CHECK-NEXT: vmsgtu.vx v25, v26, a0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <32 x i8>, <32 x i8>* %x
%b = insertelement <32 x i8> undef, i8 5, i32 0
@@ -638,7 +638,7 @@ define void @setult_vi_v64i8(<64 x i8>* %x, <64 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, mu
; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: vmsleu.vi v25, v28, 4
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 5, i32 0
@@ -655,7 +655,7 @@ define void @setuge_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) {
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmsgtu.vi v25, v8, 4
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x
%b = insertelement <128 x i8> undef, i8 5, i32 0
@@ -671,7 +671,7 @@ define void @setule_vi_v8i8(<8 x i8>* %x, <8 x i1>* %z) {
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vmsleu.vi v25, v25, 5
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 5, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
index 0c537e80efdee..cb81fc9fa5ae2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
@@ -767,10 +767,10 @@ define <128 x i1> @buildvec_mask_optsize_v128i1() optsize {
; RV32-LMULMAX4-NEXT: addi a0, a0, %lo(.LCPI21_0)
; RV32-LMULMAX4-NEXT: addi a1, zero, 64
; RV32-LMULMAX4-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; RV32-LMULMAX4-NEXT: vle1.v v0, (a0)
+; RV32-LMULMAX4-NEXT: vlm.v v0, (a0)
; RV32-LMULMAX4-NEXT: lui a0, %hi(.LCPI21_1)
; RV32-LMULMAX4-NEXT: addi a0, a0, %lo(.LCPI21_1)
-; RV32-LMULMAX4-NEXT: vle1.v v8, (a0)
+; RV32-LMULMAX4-NEXT: vlm.v v8, (a0)
; RV32-LMULMAX4-NEXT: ret
;
; RV64-LMULMAX4-LABEL: buildvec_mask_optsize_v128i1:
@@ -800,7 +800,7 @@ define <128 x i1> @buildvec_mask_optsize_v128i1() optsize {
; RV32-LMULMAX8-NEXT: addi a0, a0, %lo(.LCPI21_0)
; RV32-LMULMAX8-NEXT: addi a1, zero, 128
; RV32-LMULMAX8-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; RV32-LMULMAX8-NEXT: vle1.v v0, (a0)
+; RV32-LMULMAX8-NEXT: vlm.v v0, (a0)
; RV32-LMULMAX8-NEXT: ret
;
; RV64-LMULMAX8-LABEL: buildvec_mask_optsize_v128i1:
@@ -809,7 +809,7 @@ define <128 x i1> @buildvec_mask_optsize_v128i1() optsize {
; RV64-LMULMAX8-NEXT: addi a0, a0, %lo(.LCPI21_0)
; RV64-LMULMAX8-NEXT: addi a1, zero, 128
; RV64-LMULMAX8-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; RV64-LMULMAX8-NEXT: vle1.v v0, (a0)
+; RV64-LMULMAX8-NEXT: vlm.v v0, (a0)
; RV64-LMULMAX8-NEXT: ret
ret <128 x i1> <i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 1, i1 0, i1 1, i1 1, i1 1, i1 0, i1 1, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 1, i1 1>
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
index e79e4f0c5043c..e60a1da17f843 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
@@ -8,7 +8,7 @@ define void @load_store_v1i1(<1 x i1>* %x, <1 x i1>* %y) {
; CHECK-LABEL: load_store_v1i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
+; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
@@ -17,7 +17,7 @@ define void @load_store_v1i1(<1 x i1>* %x, <1 x i1>* %y) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <1 x i1>, <1 x i1>* %x
store <1 x i1> %a, <1 x i1>* %y
@@ -28,7 +28,7 @@ define void @load_store_v2i1(<2 x i1>* %x, <2 x i1>* %y) {
; CHECK-LABEL: load_store_v2i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
+; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
@@ -37,7 +37,7 @@ define void @load_store_v2i1(<2 x i1>* %x, <2 x i1>* %y) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <2 x i1>, <2 x i1>* %x
store <2 x i1> %a, <2 x i1>* %y
@@ -48,7 +48,7 @@ define void @load_store_v4i1(<4 x i1>* %x, <4 x i1>* %y) {
; CHECK-LABEL: load_store_v4i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
+; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
@@ -57,7 +57,7 @@ define void @load_store_v4i1(<4 x i1>* %x, <4 x i1>* %y) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <4 x i1>, <4 x i1>* %x
store <4 x i1> %a, <4 x i1>* %y
@@ -68,8 +68,8 @@ define void @load_store_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
; CHECK-LABEL: load_store_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <8 x i1>, <8 x i1>* %x
store <8 x i1> %a, <8 x i1>* %y
@@ -80,8 +80,8 @@ define void @load_store_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
; CHECK-LABEL: load_store_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <16 x i1>, <16 x i1>* %x
store <16 x i1> %a, <16 x i1>* %y
@@ -93,8 +93,8 @@ define void @load_store_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; LMULMAX2-NEXT: vle1.v v25, (a0)
-; LMULMAX2-NEXT: vse1.v v25, (a1)
+; LMULMAX2-NEXT: vlm.v v25, (a0)
+; LMULMAX2-NEXT: vsm.v v25, (a1)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: load_store_v32i1:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
index e93e36a9dcbed..b4164beebb376 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
@@ -8,10 +8,10 @@ define void @and_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
; CHECK-LABEL: and_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vle1.v v26, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vlm.v v26, (a1)
; CHECK-NEXT: vmand.mm v25, v25, v26
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%a = load <8 x i1>, <8 x i1>* %x
%b = load <8 x i1>, <8 x i1>* %y
@@ -24,10 +24,10 @@ define void @or_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
; CHECK-LABEL: or_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vle1.v v26, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vlm.v v26, (a1)
; CHECK-NEXT: vmor.mm v25, v25, v26
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%a = load <16 x i1>, <16 x i1>* %x
%b = load <16 x i1>, <16 x i1>* %y
@@ -41,10 +41,10 @@ define void @xor_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vle1.v v26, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vlm.v v26, (a1)
; CHECK-NEXT: vmxor.mm v25, v25, v26
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%a = load <32 x i1>, <32 x i1>* %x
%b = load <32 x i1>, <32 x i1>* %y
@@ -58,9 +58,9 @@ define void @not_v64i1(<64 x i1>* %x, <64 x i1>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
+; CHECK-NEXT: vlm.v v25, (a0)
; CHECK-NEXT: vmnand.mm v25, v25, v25
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x
%b = load <64 x i1>, <64 x i1>* %y
@@ -73,10 +73,10 @@ define void @andnot_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
; CHECK-LABEL: andnot_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vle1.v v26, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vlm.v v26, (a1)
; CHECK-NEXT: vmandnot.mm v25, v26, v25
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%a = load <8 x i1>, <8 x i1>* %x
%b = load <8 x i1>, <8 x i1>* %y
@@ -90,10 +90,10 @@ define void @ornot_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
; CHECK-LABEL: ornot_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vle1.v v26, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vlm.v v26, (a1)
; CHECK-NEXT: vmornot.mm v25, v26, v25
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%a = load <16 x i1>, <16 x i1>* %x
%b = load <16 x i1>, <16 x i1>* %y
@@ -108,10 +108,10 @@ define void @xornot_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vle1.v v26, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vlm.v v26, (a1)
; CHECK-NEXT: vmxnor.mm v25, v25, v26
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%a = load <32 x i1>, <32 x i1>* %x
%b = load <32 x i1>, <32 x i1>* %y
@@ -125,10 +125,10 @@ define void @nand_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
; CHECK-LABEL: nand_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vle1.v v26, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vlm.v v26, (a1)
; CHECK-NEXT: vmnand.mm v25, v25, v26
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%a = load <8 x i1>, <8 x i1>* %x
%b = load <8 x i1>, <8 x i1>* %y
@@ -142,10 +142,10 @@ define void @nor_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
; CHECK-LABEL: nor_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vle1.v v26, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vlm.v v26, (a1)
; CHECK-NEXT: vmnor.mm v25, v25, v26
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%a = load <16 x i1>, <16 x i1>* %x
%b = load <16 x i1>, <16 x i1>* %y
@@ -160,10 +160,10 @@ define void @xnor_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vle1.v v26, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vlm.v v26, (a1)
; CHECK-NEXT: vmxnor.mm v25, v25, v26
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%a = load <32 x i1>, <32 x i1>* %x
%b = load <32 x i1>, <32 x i1>* %y
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
index 637037a9881db..015f6d31ea473 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
@@ -17,7 +17,7 @@ define void @splat_ones_v1i1(<1 x i1>* %x) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
store <1 x i1> <i1 1>, <1 x i1>* %x
ret void
@@ -36,7 +36,7 @@ define void @splat_zeros_v2i1(<2 x i1>* %x) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
store <2 x i1> zeroinitializer, <2 x i1>* %x
ret void
@@ -57,7 +57,7 @@ define void @splat_v1i1(<1 x i1>* %x, i1 %y) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <1 x i1> undef, i1 %y, i32 0
%b = shufflevector <1 x i1> %a, <1 x i1> undef, <1 x i32> zeroinitializer
@@ -81,7 +81,7 @@ define void @splat_v1i1_icmp(<1 x i1>* %x, i32 signext %y, i32 signext %z) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%c = icmp eq i32 %y, %z
%a = insertelement <1 x i1> undef, i1 %c, i32 0
@@ -103,7 +103,7 @@ define void @splat_ones_v4i1(<4 x i1>* %x) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
store <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i1>* %x
ret void
@@ -124,7 +124,7 @@ define void @splat_v4i1(<4 x i1>* %x, i1 %y) {
; CHECK-NEXT: vslideup.vi v26, v25, 0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vi v25, v26, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <4 x i1> undef, i1 %y, i32 0
%b = shufflevector <4 x i1> %a, <4 x i1> undef, <4 x i32> zeroinitializer
@@ -137,7 +137,7 @@ define void @splat_zeros_v8i1(<8 x i1>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmclr.m v25
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
store <8 x i1> zeroinitializer, <8 x i1>* %x
ret void
@@ -150,7 +150,7 @@ define void @splat_v8i1(<8 x i1>* %x, i1 %y) {
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <8 x i1> undef, i1 %y, i32 0
%b = shufflevector <8 x i1> %a, <8 x i1> undef, <8 x i32> zeroinitializer
@@ -163,7 +163,7 @@ define void @splat_ones_v16i1(<16 x i1>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vmset.m v25
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
store <16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <16 x i1>* %x
ret void
@@ -176,7 +176,7 @@ define void @splat_v16i1(<16 x i1>* %x, i1 %y) {
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: vmsne.vi v25, v25, 0
-; CHECK-NEXT: vse1.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a0)
; CHECK-NEXT: ret
%a = insertelement <16 x i1> undef, i1 %y, i32 0
%b = shufflevector <16 x i1> %a, <16 x i1> undef, <16 x i32> zeroinitializer
@@ -190,25 +190,25 @@ define void @splat_zeros_v32i1(<32 x i1>* %x) {
; LMULMAX2-NEXT: addi a1, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; LMULMAX2-NEXT: vmclr.m v25
-; LMULMAX2-NEXT: vse1.v v25, (a0)
+; LMULMAX2-NEXT: vsm.v v25, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: splat_zeros_v32i1:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmclr.m v25
-; LMULMAX1-RV32-NEXT: vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vsm.v v25, (a0)
; LMULMAX1-RV32-NEXT: addi a0, a0, 2
-; LMULMAX1-RV32-NEXT: vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vsm.v v25, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: splat_zeros_v32i1:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV64-NEXT: vmclr.m v25
-; LMULMAX1-RV64-NEXT: vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vsm.v v25, (a0)
; LMULMAX1-RV64-NEXT: addi a0, a0, 2
-; LMULMAX1-RV64-NEXT: vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vsm.v v25, (a0)
; LMULMAX1-RV64-NEXT: ret
store <32 x i1> zeroinitializer, <32 x i1>* %x
ret void
@@ -222,7 +222,7 @@ define void @splat_v32i1(<32 x i1>* %x, i1 %y) {
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; LMULMAX2-NEXT: vmv.v.x v26, a1
; LMULMAX2-NEXT: vmsne.vi v25, v26, 0
-; LMULMAX2-NEXT: vse1.v v25, (a0)
+; LMULMAX2-NEXT: vsm.v v25, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: splat_v32i1:
@@ -232,8 +232,8 @@ define void @splat_v32i1(<32 x i1>* %x, i1 %y) {
; LMULMAX1-RV32-NEXT: vmv.v.x v25, a1
; LMULMAX1-RV32-NEXT: vmsne.vi v25, v25, 0
; LMULMAX1-RV32-NEXT: addi a1, a0, 2
-; LMULMAX1-RV32-NEXT: vse1.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vsm.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vsm.v v25, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: splat_v32i1:
@@ -243,8 +243,8 @@ define void @splat_v32i1(<32 x i1>* %x, i1 %y) {
; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1
; LMULMAX1-RV64-NEXT: vmsne.vi v25, v25, 0
; LMULMAX1-RV64-NEXT: addi a1, a0, 2
-; LMULMAX1-RV64-NEXT: vse1.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vsm.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vsm.v v25, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = insertelement <32 x i1> undef, i1 %y, i32 0
%b = shufflevector <32 x i1> %a, <32 x i1> undef, <32 x i32> zeroinitializer
@@ -259,34 +259,34 @@ define void @splat_ones_v64i1(<64 x i1>* %x) {
; LMULMAX2-NEXT: addi a2, zero, 32
; LMULMAX2-NEXT: vsetvli zero, a2, e8, m2, ta, mu
; LMULMAX2-NEXT: vmset.m v25
-; LMULMAX2-NEXT: vse1.v v25, (a1)
-; LMULMAX2-NEXT: vse1.v v25, (a0)
+; LMULMAX2-NEXT: vsm.v v25, (a1)
+; LMULMAX2-NEXT: vsm.v v25, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: splat_ones_v64i1:
; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV32-NEXT: vmset.m v25
-; LMULMAX1-RV32-NEXT: vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vsm.v v25, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 6
-; LMULMAX1-RV32-NEXT: vse1.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vsm.v v25, (a1)
; LMULMAX1-RV32-NEXT: addi a1, a0, 4
-; LMULMAX1-RV32-NEXT: vse1.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vsm.v v25, (a1)
; LMULMAX1-RV32-NEXT: addi a0, a0, 2
-; LMULMAX1-RV32-NEXT: vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vsm.v v25, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: splat_ones_v64i1:
; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; LMULMAX1-RV64-NEXT: vmset.m v25
-; LMULMAX1-RV64-NEXT: vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vsm.v v25, (a0)
; LMULMAX1-RV64-NEXT: addi a1, a0, 6
-; LMULMAX1-RV64-NEXT: vse1.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vsm.v v25, (a1)
; LMULMAX1-RV64-NEXT: addi a1, a0, 4
-; LMULMAX1-RV64-NEXT: vse1.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vsm.v v25, (a1)
; LMULMAX1-RV64-NEXT: addi a0, a0, 2
-; LMULMAX1-RV64-NEXT: vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vsm.v v25, (a0)
; LMULMAX1-RV64-NEXT: ret
store <64 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <64 x i1>* %x
ret void
@@ -301,8 +301,8 @@ define void @splat_v64i1(<64 x i1>* %x, i1 %y) {
; LMULMAX2-NEXT: vmv.v.x v26, a1
; LMULMAX2-NEXT: vmsne.vi v25, v26, 0
; LMULMAX2-NEXT: addi a1, a0, 4
-; LMULMAX2-NEXT: vse1.v v25, (a1)
-; LMULMAX2-NEXT: vse1.v v25, (a0)
+; LMULMAX2-NEXT: vsm.v v25, (a1)
+; LMULMAX2-NEXT: vsm.v v25, (a0)
; LMULMAX2-NEXT: ret
;
; LMULMAX1-RV32-LABEL: splat_v64i1:
@@ -312,12 +312,12 @@ define void @splat_v64i1(<64 x i1>* %x, i1 %y) {
; LMULMAX1-RV32-NEXT: vmv.v.x v25, a1
; LMULMAX1-RV32-NEXT: vmsne.vi v25, v25, 0
; LMULMAX1-RV32-NEXT: addi a1, a0, 6
-; LMULMAX1-RV32-NEXT: vse1.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vsm.v v25, (a1)
; LMULMAX1-RV32-NEXT: addi a1, a0, 4
-; LMULMAX1-RV32-NEXT: vse1.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vsm.v v25, (a1)
; LMULMAX1-RV32-NEXT: addi a1, a0, 2
-; LMULMAX1-RV32-NEXT: vse1.v v25, (a1)
-; LMULMAX1-RV32-NEXT: vse1.v v25, (a0)
+; LMULMAX1-RV32-NEXT: vsm.v v25, (a1)
+; LMULMAX1-RV32-NEXT: vsm.v v25, (a0)
; LMULMAX1-RV32-NEXT: ret
;
; LMULMAX1-RV64-LABEL: splat_v64i1:
@@ -327,12 +327,12 @@ define void @splat_v64i1(<64 x i1>* %x, i1 %y) {
; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1
; LMULMAX1-RV64-NEXT: vmsne.vi v25, v25, 0
; LMULMAX1-RV64-NEXT: addi a1, a0, 6
-; LMULMAX1-RV64-NEXT: vse1.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vsm.v v25, (a1)
; LMULMAX1-RV64-NEXT: addi a1, a0, 4
-; LMULMAX1-RV64-NEXT: vse1.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vsm.v v25, (a1)
; LMULMAX1-RV64-NEXT: addi a1, a0, 2
-; LMULMAX1-RV64-NEXT: vse1.v v25, (a1)
-; LMULMAX1-RV64-NEXT: vse1.v v25, (a0)
+; LMULMAX1-RV64-NEXT: vsm.v v25, (a1)
+; LMULMAX1-RV64-NEXT: vsm.v v25, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = insertelement <64 x i1> undef, i1 %y, i32 0
%b = shufflevector <64 x i1> %a, <64 x i1> undef, <64 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
index c0dc7fb97a98c..741bd68bf855f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
@@ -85,7 +85,7 @@ define <2 x i16> @mgather_v2i16_align1(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16>
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmsne.vi v25, v26, 0
; RV32-NEXT: addi a0, sp, 15
-; RV32-NEXT: vse1.v v25, (a0)
+; RV32-NEXT: vsm.v v25, (a0)
; RV32-NEXT: lbu a0, 15(sp)
; RV32-NEXT: andi a1, a0, 1
; RV32-NEXT: beqz a1, .LBB4_2
@@ -132,7 +132,7 @@ define <2 x i16> @mgather_v2i16_align1(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16>
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmsne.vi v25, v26, 0
; RV64-NEXT: addi a0, sp, 15
-; RV64-NEXT: vse1.v v25, (a0)
+; RV64-NEXT: vsm.v v25, (a0)
; RV64-NEXT: lbu a0, 15(sp)
; RV64-NEXT: andi a1, a0, 1
; RV64-NEXT: beqz a1, .LBB4_2
@@ -185,7 +185,7 @@ define <2 x i64> @mgather_v2i64_align4(<2 x i64*> %ptrs, <2 x i1> %m, <2 x i64>
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmsne.vi v25, v26, 0
; RV32-NEXT: addi a0, sp, 15
-; RV32-NEXT: vse1.v v25, (a0)
+; RV32-NEXT: vsm.v v25, (a0)
; RV32-NEXT: lbu a0, 15(sp)
; RV32-NEXT: andi a1, a0, 1
; RV32-NEXT: vsetivli zero, 2, e32, m1, ta, mu
@@ -232,7 +232,7 @@ define <2 x i64> @mgather_v2i64_align4(<2 x i64*> %ptrs, <2 x i1> %m, <2 x i64>
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmsne.vi v25, v26, 0
; RV64-NEXT: addi a0, sp, 15
-; RV64-NEXT: vse1.v v25, (a0)
+; RV64-NEXT: vsm.v v25, (a0)
; RV64-NEXT: lbu a0, 15(sp)
; RV64-NEXT: andi a1, a0, 1
; RV64-NEXT: beqz a1, .LBB5_2
@@ -285,7 +285,7 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmsne.vi v25, v26, 0
; RV32-NEXT: addi a0, sp, 15
-; RV32-NEXT: vse1.v v25, (a0)
+; RV32-NEXT: vsm.v v25, (a0)
; RV32-NEXT: lbu a0, 15(sp)
; RV32-NEXT: andi a1, a0, 1
; RV32-NEXT: bnez a1, .LBB6_5
@@ -362,7 +362,7 @@ define void @mscatter_v4i16_align1(<4 x i16> %val, <4 x i16*> %ptrs, <4 x i1> %m
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmsne.vi v25, v26, 0
; RV64-NEXT: addi a0, sp, 15
-; RV64-NEXT: vse1.v v25, (a0)
+; RV64-NEXT: vsm.v v25, (a0)
; RV64-NEXT: lbu a0, 15(sp)
; RV64-NEXT: andi a1, a0, 1
; RV64-NEXT: bnez a1, .LBB6_5
@@ -445,7 +445,7 @@ define void @mscatter_v2i32_align2(<2 x i32> %val, <2 x i32*> %ptrs, <2 x i1> %m
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmsne.vi v25, v26, 0
; RV32-NEXT: addi a0, sp, 15
-; RV32-NEXT: vse1.v v25, (a0)
+; RV32-NEXT: vsm.v v25, (a0)
; RV32-NEXT: lbu a0, 15(sp)
; RV32-NEXT: andi a1, a0, 1
; RV32-NEXT: bnez a1, .LBB7_3
@@ -490,7 +490,7 @@ define void @mscatter_v2i32_align2(<2 x i32> %val, <2 x i32*> %ptrs, <2 x i1> %m
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmsne.vi v25, v26, 0
; RV64-NEXT: addi a0, sp, 15
-; RV64-NEXT: vse1.v v25, (a0)
+; RV64-NEXT: vsm.v v25, (a0)
; RV64-NEXT: lbu a0, 15(sp)
; RV64-NEXT: andi a1, a0, 1
; RV64-NEXT: bnez a1, .LBB7_3
@@ -544,7 +544,7 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmsne.vi v25, v26, 0
; RV32-NEXT: addi a2, sp, 15
-; RV32-NEXT: vse1.v v25, (a2)
+; RV32-NEXT: vsm.v v25, (a2)
; RV32-NEXT: lbu a2, 15(sp)
; RV32-NEXT: andi a3, a2, 1
; RV32-NEXT: beqz a3, .LBB8_2
@@ -604,7 +604,7 @@ define void @masked_load_v2i32_align1(<2 x i32>* %a, <2 x i32> %m, <2 x i32>* %r
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmsne.vi v25, v26, 0
; RV64-NEXT: addi a2, sp, 15
-; RV64-NEXT: vse1.v v25, (a2)
+; RV64-NEXT: vsm.v v25, (a2)
; RV64-NEXT: lbu a2, 15(sp)
; RV64-NEXT: andi a3, a2, 1
; RV64-NEXT: beqz a3, .LBB8_2
@@ -672,7 +672,7 @@ define void @masked_store_v2i32_align2(<2 x i32> %val, <2 x i32>* %a, <2 x i32>
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vmsne.vi v25, v26, 0
; RV32-NEXT: addi a1, sp, 15
-; RV32-NEXT: vse1.v v25, (a1)
+; RV32-NEXT: vsm.v v25, (a1)
; RV32-NEXT: lbu a1, 15(sp)
; RV32-NEXT: andi a2, a1, 1
; RV32-NEXT: bnez a2, .LBB9_3
@@ -715,7 +715,7 @@ define void @masked_store_v2i32_align2(<2 x i32> %val, <2 x i32>* %a, <2 x i32>
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vmsne.vi v25, v26, 0
; RV64-NEXT: addi a1, sp, 15
-; RV64-NEXT: vse1.v v25, (a1)
+; RV64-NEXT: vsm.v v25, (a1)
; RV64-NEXT: lbu a1, 15(sp)
; RV64-NEXT: andi a2, a1, 1
; RV64-NEXT: bnez a2, .LBB9_3
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
index 7fdd3255e0ff0..b7fb68b14ffcc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
@@ -403,7 +403,7 @@ define <256 x i8> @vadd_vi_v258i8(<256 x i8> %va, <256 x i1> %m, i32 zeroext %ev
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu
-; CHECK-NEXT: vle1.v v26, (a0)
+; CHECK-NEXT: vlm.v v26, (a0)
; CHECK-NEXT: addi a3, a1, -128
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: mv a0, zero
@@ -462,7 +462,7 @@ define <256 x i8> @vadd_vi_v258i8_evl129(<256 x i8> %va, <256 x i1> %m) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
+; CHECK-NEXT: vlm.v v25, (a0)
; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t
; CHECK-NEXT: vsetivli zero, 1, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v25
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
index 087504cf84b2e..e6ae1cee619c9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
@@ -7,7 +7,7 @@ define void @vselect_vv_v8i32(<8 x i32>* %a, <8 x i32>* %b, <8 x i1>* %cc, <8 x
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vle1.v v0, (a2)
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle32.v v28, (a1)
; CHECK-NEXT: vmerge.vvm v26, v28, v26, v0
; CHECK-NEXT: vse32.v v26, (a3)
@@ -24,7 +24,7 @@ define void @vselect_vx_v8i32(i32 %a, <8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* %
; CHECK-LABEL: vselect_vx_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle1.v v0, (a2)
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle32.v v26, (a1)
; CHECK-NEXT: vmerge.vxm v26, v26, a0, v0
; CHECK-NEXT: vse32.v v26, (a3)
@@ -42,7 +42,7 @@ define void @vselect_vi_v8i32(<8 x i32>* %b, <8 x i1>* %cc, <8 x i32>* %z) {
; CHECK-LABEL: vselect_vi_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle1.v v0, (a1)
+; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vle32.v v26, (a0)
; CHECK-NEXT: vmerge.vim v26, v26, -1, v0
; CHECK-NEXT: vse32.v v26, (a2)
@@ -61,7 +61,7 @@ define void @vselect_vv_v8f32(<8 x float>* %a, <8 x float>* %b, <8 x i1>* %cc, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vle32.v v26, (a0)
-; CHECK-NEXT: vle1.v v0, (a2)
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle32.v v28, (a1)
; CHECK-NEXT: vmerge.vvm v26, v28, v26, v0
; CHECK-NEXT: vse32.v v26, (a3)
@@ -78,7 +78,7 @@ define void @vselect_vx_v8f32(float %a, <8 x float>* %b, <8 x i1>* %cc, <8 x flo
; CHECK-LABEL: vselect_vx_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle1.v v0, (a1)
+; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vle32.v v26, (a0)
; CHECK-NEXT: vfmerge.vfm v26, v26, fa0, v0
; CHECK-NEXT: vse32.v v26, (a2)
@@ -96,7 +96,7 @@ define void @vselect_vfpzero_v8f32(<8 x float>* %b, <8 x i1>* %cc, <8 x float>*
; CHECK-LABEL: vselect_vfpzero_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
-; CHECK-NEXT: vle1.v v0, (a1)
+; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vle32.v v26, (a0)
; CHECK-NEXT: vmerge.vim v26, v26, 0, v0
; CHECK-NEXT: vse32.v v26, (a2)
@@ -115,7 +115,7 @@ define void @vselect_vv_v16i16(<16 x i16>* %a, <16 x i16>* %b, <16 x i1>* %cc, <
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vle16.v v26, (a0)
-; CHECK-NEXT: vle1.v v0, (a2)
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle16.v v28, (a1)
; CHECK-NEXT: vmerge.vvm v26, v28, v26, v0
; CHECK-NEXT: vse16.v v26, (a3)
@@ -132,7 +132,7 @@ define void @vselect_vx_v16i16(i16 signext %a, <16 x i16>* %b, <16 x i1>* %cc, <
; CHECK-LABEL: vselect_vx_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle1.v v0, (a2)
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle16.v v26, (a1)
; CHECK-NEXT: vmerge.vxm v26, v26, a0, v0
; CHECK-NEXT: vse16.v v26, (a3)
@@ -150,7 +150,7 @@ define void @vselect_vi_v16i16(<16 x i16>* %b, <16 x i1>* %cc, <16 x i16>* %z) {
; CHECK-LABEL: vselect_vi_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
-; CHECK-NEXT: vle1.v v0, (a1)
+; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: vmerge.vim v26, v26, 4, v0
; CHECK-NEXT: vse16.v v26, (a2)
@@ -170,7 +170,7 @@ define void @vselect_vv_v32f16(<32 x half>* %a, <32 x half>* %b, <32 x i1>* %cc,
; CHECK-NEXT: addi a4, zero, 32
; CHECK-NEXT: vsetvli zero, a4, e16, m4, ta, mu
; CHECK-NEXT: vle16.v v28, (a0)
-; CHECK-NEXT: vle1.v v0, (a2)
+; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: vle16.v v8, (a1)
; CHECK-NEXT: vmerge.vvm v28, v8, v28, v0
; CHECK-NEXT: vse16.v v28, (a3)
@@ -188,7 +188,7 @@ define void @vselect_vx_v32f16(half %a, <32 x half>* %b, <32 x i1>* %cc, <32 x h
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu
-; CHECK-NEXT: vle1.v v0, (a1)
+; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vfmerge.vfm v28, v28, fa0, v0
; CHECK-NEXT: vse16.v v28, (a2)
@@ -207,7 +207,7 @@ define void @vselect_vfpzero_v32f16(<32 x half>* %b, <32 x i1>* %cc, <32 x half>
; CHECK: # %bb.0:
; CHECK-NEXT: addi a3, zero, 32
; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, mu
-; CHECK-NEXT: vle1.v v0, (a1)
+; CHECK-NEXT: vlm.v v0, (a1)
; CHECK-NEXT: vle16.v v28, (a0)
; CHECK-NEXT: vmerge.vim v28, v28, 0, v0
; CHECK-NEXT: vse16.v v28, (a2)
diff --git a/llvm/test/CodeGen/RISCV/rvv/load-mask.ll b/llvm/test/CodeGen/RISCV/rvv/load-mask.ll
index 54b56490da190..34a3952730426 100644
--- a/llvm/test/CodeGen/RISCV/rvv/load-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/load-mask.ll
@@ -8,8 +8,8 @@ define void @test_load_mask_64(<vscale x 64 x i1>* %pa, <vscale x 64 x i1>* %pb)
; CHECK-LABEL: test_load_mask_64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m8, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <vscale x 64 x i1>, <vscale x 64 x i1>* %pa
store <vscale x 64 x i1> %a, <vscale x 64 x i1>* %pb
@@ -20,8 +20,8 @@ define void @test_load_mask_32(<vscale x 32 x i1>* %pa, <vscale x 32 x i1>* %pb)
; CHECK-LABEL: test_load_mask_32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m4, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <vscale x 32 x i1>, <vscale x 32 x i1>* %pa
store <vscale x 32 x i1> %a, <vscale x 32 x i1>* %pb
@@ -32,8 +32,8 @@ define void @test_load_mask_16(<vscale x 16 x i1>* %pa, <vscale x 16 x i1>* %pb)
; CHECK-LABEL: test_load_mask_16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <vscale x 16 x i1>, <vscale x 16 x i1>* %pa
store <vscale x 16 x i1> %a, <vscale x 16 x i1>* %pb
@@ -44,8 +44,8 @@ define void @test_load_mask_8(<vscale x 8 x i1>* %pa, <vscale x 8 x i1>* %pb) {
; CHECK-LABEL: test_load_mask_8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <vscale x 8 x i1>, <vscale x 8 x i1>* %pa
store <vscale x 8 x i1> %a, <vscale x 8 x i1>* %pb
@@ -56,8 +56,8 @@ define void @test_load_mask_4(<vscale x 4 x i1>* %pa, <vscale x 4 x i1>* %pb) {
; CHECK-LABEL: test_load_mask_4:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <vscale x 4 x i1>, <vscale x 4 x i1>* %pa
store <vscale x 4 x i1> %a, <vscale x 4 x i1>* %pb
@@ -68,8 +68,8 @@ define void @test_load_mask_2(<vscale x 2 x i1>* %pa, <vscale x 2 x i1>* %pb) {
; CHECK-LABEL: test_load_mask_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <vscale x 2 x i1>, <vscale x 2 x i1>* %pa
store <vscale x 2 x i1> %a, <vscale x 2 x i1>* %pb
@@ -80,8 +80,8 @@ define void @test_load_mask_1(<vscale x 1 x i1>* %pa, <vscale x 1 x i1>* %pb) {
; CHECK-LABEL: test_load_mask_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
-; CHECK-NEXT: vse1.v v25, (a1)
+; CHECK-NEXT: vlm.v v25, (a0)
+; CHECK-NEXT: vsm.v v25, (a1)
; CHECK-NEXT: ret
%a = load <vscale x 1 x i1>, <vscale x 1 x i1>* %pa
store <vscale x 1 x i1> %a, <vscale x 1 x i1>* %pb
diff --git a/llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll b/llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
index e7f2e26bac969..97332be644e98 100644
--- a/llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
@@ -93,7 +93,7 @@ define <vscale x 1 x i1> @unaligned_load_nxv1i1_a1(<vscale x 1 x i1>* %ptr) {
; CHECK-LABEL: unaligned_load_nxv1i1_a1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
+; CHECK-NEXT: vlm.v v0, (a0)
; CHECK-NEXT: ret
%v = load <vscale x 1 x i1>, <vscale x 1 x i1>* %ptr, align 1
ret <vscale x 1 x i1> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
index 377a24b34a7e3..766ab56c40219 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
@@ -642,7 +642,7 @@ define <vscale x 128 x i8> @vadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x
; CHECK-NEXT: .LBB49_2:
; CHECK-NEXT: mv a4, zero
; CHECK-NEXT: vsetvli a5, zero, e8, m8, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
+; CHECK-NEXT: vlm.v v25, (a0)
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, mu
; CHECK-NEXT: sub a0, a1, a2
; CHECK-NEXT: vadd.vi v8, v8, -1, v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll
deleted file mode 100644
index 0c8b103c7a689..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll
+++ /dev/null
@@ -1,94 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-
-declare <vscale x 1 x i1> @llvm.riscv.vle1.nxv1i1(<vscale x 1 x i1>*, i32);
-
-define <vscale x 1 x i1> @intrinsic_vle1_v_nxv1i1(<vscale x 1 x i1>* %0, i32 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv1i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vle1.nxv1i1(<vscale x 1 x i1>* %0, i32 %1)
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vle1.nxv2i1(<vscale x 2 x i1>*, i32);
-
-define <vscale x 2 x i1> @intrinsic_vle1_v_nxv2i1(<vscale x 2 x i1>* %0, i32 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv2i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vle1.nxv2i1(<vscale x 2 x i1>* %0, i32 %1)
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vle1.nxv4i1(<vscale x 4 x i1>*, i32);
-
-define <vscale x 4 x i1> @intrinsic_vle1_v_nxv4i1(<vscale x 4 x i1>* %0, i32 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv4i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vle1.nxv4i1(<vscale x 4 x i1>* %0, i32 %1)
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vle1.nxv8i1(<vscale x 8 x i1>*, i32);
-
-define <vscale x 8 x i1> @intrinsic_vle1_v_nxv8i1(<vscale x 8 x i1>* %0, i32 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv8i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vle1.nxv8i1(<vscale x 8 x i1>* %0, i32 %1)
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vle1.nxv16i1(<vscale x 16 x i1>*, i32);
-
-define <vscale x 16 x i1> @intrinsic_vle1_v_nxv16i1(<vscale x 16 x i1>* %0, i32 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv16i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vle1.nxv16i1(<vscale x 16 x i1>* %0, i32 %1)
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 32 x i1> @llvm.riscv.vle1.nxv32i1(<vscale x 32 x i1>*, i32);
-
-define <vscale x 32 x i1> @intrinsic_vle1_v_nxv32i1(<vscale x 32 x i1>* %0, i32 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv32i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i1> @llvm.riscv.vle1.nxv32i1(<vscale x 32 x i1>* %0, i32 %1)
- ret <vscale x 32 x i1> %a
-}
-
-declare <vscale x 64 x i1> @llvm.riscv.vle1.nxv64i1(<vscale x 64 x i1>*, i32);
-
-define <vscale x 64 x i1> @intrinsic_vle1_v_nxv64i1(<vscale x 64 x i1>* %0, i32 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv64i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i1> @llvm.riscv.vle1.nxv64i1(<vscale x 64 x i1>* %0, i32 %1)
- ret <vscale x 64 x i1> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll
deleted file mode 100644
index 645b757c1994f..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll
+++ /dev/null
@@ -1,94 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-
-declare <vscale x 1 x i1> @llvm.riscv.vle1.nxv1i1(<vscale x 1 x i1>*, i64);
-
-define <vscale x 1 x i1> @intrinsic_vle1_v_nxv1i1(<vscale x 1 x i1>* %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv1i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vle1.nxv1i1(<vscale x 1 x i1>* %0, i64 %1)
- ret <vscale x 1 x i1> %a
-}
-
-declare <vscale x 2 x i1> @llvm.riscv.vle1.nxv2i1(<vscale x 2 x i1>*, i64);
-
-define <vscale x 2 x i1> @intrinsic_vle1_v_nxv2i1(<vscale x 2 x i1>* %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv2i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 2 x i1> @llvm.riscv.vle1.nxv2i1(<vscale x 2 x i1>* %0, i64 %1)
- ret <vscale x 2 x i1> %a
-}
-
-declare <vscale x 4 x i1> @llvm.riscv.vle1.nxv4i1(<vscale x 4 x i1>*, i64);
-
-define <vscale x 4 x i1> @intrinsic_vle1_v_nxv4i1(<vscale x 4 x i1>* %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv4i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 4 x i1> @llvm.riscv.vle1.nxv4i1(<vscale x 4 x i1>* %0, i64 %1)
- ret <vscale x 4 x i1> %a
-}
-
-declare <vscale x 8 x i1> @llvm.riscv.vle1.nxv8i1(<vscale x 8 x i1>*, i64);
-
-define <vscale x 8 x i1> @intrinsic_vle1_v_nxv8i1(<vscale x 8 x i1>* %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv8i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 8 x i1> @llvm.riscv.vle1.nxv8i1(<vscale x 8 x i1>* %0, i64 %1)
- ret <vscale x 8 x i1> %a
-}
-
-declare <vscale x 16 x i1> @llvm.riscv.vle1.nxv16i1(<vscale x 16 x i1>*, i64);
-
-define <vscale x 16 x i1> @intrinsic_vle1_v_nxv16i1(<vscale x 16 x i1>* %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv16i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 16 x i1> @llvm.riscv.vle1.nxv16i1(<vscale x 16 x i1>* %0, i64 %1)
- ret <vscale x 16 x i1> %a
-}
-
-declare <vscale x 32 x i1> @llvm.riscv.vle1.nxv32i1(<vscale x 32 x i1>*, i64);
-
-define <vscale x 32 x i1> @intrinsic_vle1_v_nxv32i1(<vscale x 32 x i1>* %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv32i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 32 x i1> @llvm.riscv.vle1.nxv32i1(<vscale x 32 x i1>* %0, i64 %1)
- ret <vscale x 32 x i1> %a
-}
-
-declare <vscale x 64 x i1> @llvm.riscv.vle1.nxv64i1(<vscale x 64 x i1>*, i64);
-
-define <vscale x 64 x i1> @intrinsic_vle1_v_nxv64i1(<vscale x 64 x i1>* %0, i64 %1) nounwind {
-; CHECK-LABEL: intrinsic_vle1_v_nxv64i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vle1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 64 x i1> @llvm.riscv.vle1.nxv64i1(<vscale x 64 x i1>* %0, i64 %1)
- ret <vscale x 64 x i1> %a
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vlm-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vlm-rv32.ll
new file mode 100644
index 0000000000000..b7933dd4c9b93
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vlm-rv32.ll
@@ -0,0 +1,94 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN: < %s | FileCheck %s
+
+declare <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(<vscale x 1 x i1>*, i32);
+
+define <vscale x 1 x i1> @intrinsic_vlm_v_nxv1i1(<vscale x 1 x i1>* %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv1i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
+; CHECK-NEXT: vlm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(<vscale x 1 x i1>* %0, i32 %1)
+ ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(<vscale x 2 x i1>*, i32);
+
+define <vscale x 2 x i1> @intrinsic_vlm_v_nxv2i1(<vscale x 2 x i1>* %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv2i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
+; CHECK-NEXT: vlm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(<vscale x 2 x i1>* %0, i32 %1)
+ ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(<vscale x 4 x i1>*, i32);
+
+define <vscale x 4 x i1> @intrinsic_vlm_v_nxv4i1(<vscale x 4 x i1>* %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv4i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
+; CHECK-NEXT: vlm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(<vscale x 4 x i1>* %0, i32 %1)
+ ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(<vscale x 8 x i1>*, i32);
+
+define <vscale x 8 x i1> @intrinsic_vlm_v_nxv8i1(<vscale x 8 x i1>* %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv8i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
+; CHECK-NEXT: vlm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(<vscale x 8 x i1>* %0, i32 %1)
+ ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(<vscale x 16 x i1>*, i32);
+
+define <vscale x 16 x i1> @intrinsic_vlm_v_nxv16i1(<vscale x 16 x i1>* %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv16i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
+; CHECK-NEXT: vlm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(<vscale x 16 x i1>* %0, i32 %1)
+ ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(<vscale x 32 x i1>*, i32);
+
+define <vscale x 32 x i1> @intrinsic_vlm_v_nxv32i1(<vscale x 32 x i1>* %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv32i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
+; CHECK-NEXT: vlm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(<vscale x 32 x i1>* %0, i32 %1)
+ ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(<vscale x 64 x i1>*, i32);
+
+define <vscale x 64 x i1> @intrinsic_vlm_v_nxv64i1(<vscale x 64 x i1>* %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv64i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
+; CHECK-NEXT: vlm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(<vscale x 64 x i1>* %0, i32 %1)
+ ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vlm-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vlm-rv64.ll
new file mode 100644
index 0000000000000..2a969a7ae445a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vlm-rv64.ll
@@ -0,0 +1,94 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN: < %s | FileCheck %s
+
+declare <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(<vscale x 1 x i1>*, i64);
+
+define <vscale x 1 x i1> @intrinsic_vlm_v_nxv1i1(<vscale x 1 x i1>* %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv1i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
+; CHECK-NEXT: vlm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x i1> @llvm.riscv.vlm.nxv1i1(<vscale x 1 x i1>* %0, i64 %1)
+ ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(<vscale x 2 x i1>*, i64);
+
+define <vscale x 2 x i1> @intrinsic_vlm_v_nxv2i1(<vscale x 2 x i1>* %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv2i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
+; CHECK-NEXT: vlm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x i1> @llvm.riscv.vlm.nxv2i1(<vscale x 2 x i1>* %0, i64 %1)
+ ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(<vscale x 4 x i1>*, i64);
+
+define <vscale x 4 x i1> @intrinsic_vlm_v_nxv4i1(<vscale x 4 x i1>* %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv4i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
+; CHECK-NEXT: vlm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x i1> @llvm.riscv.vlm.nxv4i1(<vscale x 4 x i1>* %0, i64 %1)
+ ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(<vscale x 8 x i1>*, i64);
+
+define <vscale x 8 x i1> @intrinsic_vlm_v_nxv8i1(<vscale x 8 x i1>* %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv8i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
+; CHECK-NEXT: vlm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x i1> @llvm.riscv.vlm.nxv8i1(<vscale x 8 x i1>* %0, i64 %1)
+ ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(<vscale x 16 x i1>*, i64);
+
+define <vscale x 16 x i1> @intrinsic_vlm_v_nxv16i1(<vscale x 16 x i1>* %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv16i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
+; CHECK-NEXT: vlm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 16 x i1> @llvm.riscv.vlm.nxv16i1(<vscale x 16 x i1>* %0, i64 %1)
+ ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(<vscale x 32 x i1>*, i64);
+
+define <vscale x 32 x i1> @intrinsic_vlm_v_nxv32i1(<vscale x 32 x i1>* %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv32i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
+; CHECK-NEXT: vlm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 32 x i1> @llvm.riscv.vlm.nxv32i1(<vscale x 32 x i1>* %0, i64 %1)
+ ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(<vscale x 64 x i1>*, i64);
+
+define <vscale x 64 x i1> @intrinsic_vlm_v_nxv64i1(<vscale x 64 x i1>* %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vlm_v_nxv64i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
+; CHECK-NEXT: vlm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 64 x i1> @llvm.riscv.vlm.nxv64i1(<vscale x 64 x i1>* %0, i64 %1)
+ ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll
deleted file mode 100644
index 3943bf81f3459..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll
+++ /dev/null
@@ -1,137 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-
-declare void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>*, i32);
-
-define void @intrinsic_vse1_v_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv1i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- call void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i32 %2)
- ret void
-}
-
-declare void @llvm.riscv.vse1.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>*, i32);
-
-define void @intrinsic_vse1_v_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv2i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- call void @llvm.riscv.vse1.nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i32 %2)
- ret void
-}
-
-declare void @llvm.riscv.vse1.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>*, i32);
-
-define void @intrinsic_vse1_v_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv4i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- call void @llvm.riscv.vse1.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i32 %2)
- ret void
-}
-
-declare void @llvm.riscv.vse1.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>*, i32);
-
-define void @intrinsic_vse1_v_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv8i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- call void @llvm.riscv.vse1.nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i32 %2)
- ret void
-}
-
-declare void @llvm.riscv.vse1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>*, i32);
-
-define void @intrinsic_vse1_v_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv16i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- call void @llvm.riscv.vse1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i32 %2)
- ret void
-}
-
-declare void @llvm.riscv.vse1.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>*, i32);
-
-define void @intrinsic_vse1_v_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv32i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- call void @llvm.riscv.vse1.nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i32 %2)
- ret void
-}
-
-declare void @llvm.riscv.vse1.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>*, i32);
-
-define void @intrinsic_vse1_v_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i32 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv64i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- call void @llvm.riscv.vse1.nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i32 %2)
- ret void
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i32);
-
-; Make sure we can use the vsetvli from the producing instruction.
-define void @test_vsetvli_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1>* %2, i32 %3) nounwind {
-; CHECK-LABEL: test_vsetvli_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vse1.v v25, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i32 %3)
- call void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i32 %3)
- ret void
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i32);
-
-define void @test_vsetvli_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1>* %2, i32 %3) nounwind {
-; CHECK-LABEL: test_vsetvli_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vse1.v v25, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i32 %3)
- call void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i32 %3)
- ret void
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll
deleted file mode 100644
index 2132ad1b9a960..0000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll
+++ /dev/null
@@ -1,137 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
-; RUN: < %s | FileCheck %s
-
-declare void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>*, i64);
-
-define void @intrinsic_vse1_v_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv1i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- call void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i64 %2)
- ret void
-}
-
-declare void @llvm.riscv.vse1.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>*, i64);
-
-define void @intrinsic_vse1_v_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv2i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- call void @llvm.riscv.vse1.nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i64 %2)
- ret void
-}
-
-declare void @llvm.riscv.vse1.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>*, i64);
-
-define void @intrinsic_vse1_v_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv4i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- call void @llvm.riscv.vse1.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i64 %2)
- ret void
-}
-
-declare void @llvm.riscv.vse1.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>*, i64);
-
-define void @intrinsic_vse1_v_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv8i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- call void @llvm.riscv.vse1.nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i64 %2)
- ret void
-}
-
-declare void @llvm.riscv.vse1.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>*, i64);
-
-define void @intrinsic_vse1_v_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv16i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- call void @llvm.riscv.vse1.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i64 %2)
- ret void
-}
-
-declare void @llvm.riscv.vse1.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>*, i64);
-
-define void @intrinsic_vse1_v_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv32i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- call void @llvm.riscv.vse1.nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i64 %2)
- ret void
-}
-
-declare void @llvm.riscv.vse1.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>*, i64);
-
-define void @intrinsic_vse1_v_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i64 %2) nounwind {
-; CHECK-LABEL: intrinsic_vse1_v_nxv64i1:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
-; CHECK-NEXT: vse1.v v0, (a0)
-; CHECK-NEXT: ret
-entry:
- call void @llvm.riscv.vse1.nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i64 %2)
- ret void
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
- <vscale x 1 x i16>,
- <vscale x 1 x i16>,
- i64);
-
-; Make sure we can use the vsetvli from the producing instruction.
-define void @test_vsetvli_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1>* %2, i64 %3) nounwind {
-; CHECK-LABEL: test_vsetvli_i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vse1.v v25, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
- <vscale x 1 x i16> %0,
- <vscale x 1 x i16> %1,
- i64 %3)
- call void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i64 %3)
- ret void
-}
-
-declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
- <vscale x 1 x i32>,
- <vscale x 1 x i32>,
- i64);
-
-define void @test_vsetvli_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1>* %2, i64 %3) nounwind {
-; CHECK-LABEL: test_vsetvli_i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
-; CHECK-NEXT: vmseq.vv v25, v8, v9
-; CHECK-NEXT: vse1.v v25, (a0)
-; CHECK-NEXT: ret
-entry:
- %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
- <vscale x 1 x i32> %0,
- <vscale x 1 x i32> %1,
- i64 %3)
- call void @llvm.riscv.vse1.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i64 %3)
- ret void
-}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
index 7713e2569851b..cb03f962215db 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
@@ -435,7 +435,7 @@ define void @vselect_legalize_regression(<vscale x 16 x double> %a, <vscale x 16
; CHECK-LABEL: vselect_legalize_regression:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
+; CHECK-NEXT: vlm.v v25, (a0)
; CHECK-NEXT: vmand.mm v1, v0, v25
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a2, a0, 3
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
index fb9517afc04b2..1363412dbdffc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
@@ -435,7 +435,7 @@ define void @vselect_legalize_regression(<vscale x 16 x double> %a, <vscale x 16
; CHECK-LABEL: vselect_legalize_regression:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, mu
-; CHECK-NEXT: vle1.v v25, (a0)
+; CHECK-NEXT: vlm.v v25, (a0)
; CHECK-NEXT: vmand.mm v1, v0, v25
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a2, a0, 3
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll
new file mode 100644
index 0000000000000..51a15cd9b2059
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll
@@ -0,0 +1,137 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN: < %s | FileCheck %s
+
+declare void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>*, i32);
+
+define void @intrinsic_vsm_v_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv1i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
+; CHECK-NEXT: vsm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i32 %2)
+ ret void
+}
+
+declare void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>*, i32);
+
+define void @intrinsic_vsm_v_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv2i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
+; CHECK-NEXT: vsm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i32 %2)
+ ret void
+}
+
+declare void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>*, i32);
+
+define void @intrinsic_vsm_v_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv4i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
+; CHECK-NEXT: vsm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i32 %2)
+ ret void
+}
+
+declare void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>*, i32);
+
+define void @intrinsic_vsm_v_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv8i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
+; CHECK-NEXT: vsm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i32 %2)
+ ret void
+}
+
+declare void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>*, i32);
+
+define void @intrinsic_vsm_v_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv16i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
+; CHECK-NEXT: vsm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i32 %2)
+ ret void
+}
+
+declare void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>*, i32);
+
+define void @intrinsic_vsm_v_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv32i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
+; CHECK-NEXT: vsm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i32 %2)
+ ret void
+}
+
+declare void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>*, i32);
+
+define void @intrinsic_vsm_v_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv64i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
+; CHECK-NEXT: vsm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i32 %2)
+ ret void
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
+ <vscale x 1 x i16>,
+ <vscale x 1 x i16>,
+ i32);
+
+; Make sure we can use the vsetvli from the producing instruction.
+define void @test_vsetvli_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1>* %2, i32 %3) nounwind {
+; CHECK-LABEL: test_vsetvli_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
+; CHECK-NEXT: vmseq.vv v25, v8, v9
+; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
+ <vscale x 1 x i16> %0,
+ <vscale x 1 x i16> %1,
+ i32 %3)
+ call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i32 %3)
+ ret void
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i32);
+
+define void @test_vsetvli_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1>* %2, i32 %3) nounwind {
+; CHECK-LABEL: test_vsetvli_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
+; CHECK-NEXT: vmseq.vv v25, v8, v9
+; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32> %1,
+ i32 %3)
+ call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i32 %3)
+ ret void
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll
new file mode 100644
index 0000000000000..a0fba4301bb4d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll
@@ -0,0 +1,137 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN: < %s | FileCheck %s
+
+declare void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1>, <vscale x 1 x i1>*, i64);
+
+define void @intrinsic_vsm_v_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv1i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
+; CHECK-NEXT: vsm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1>* %1, i64 %2)
+ ret void
+}
+
+declare void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>*, i64);
+
+define void @intrinsic_vsm_v_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv2i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
+; CHECK-NEXT: vsm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1>* %1, i64 %2)
+ ret void
+}
+
+declare void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>*, i64);
+
+define void @intrinsic_vsm_v_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv4i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
+; CHECK-NEXT: vsm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1>* %1, i64 %2)
+ ret void
+}
+
+declare void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>*, i64);
+
+define void @intrinsic_vsm_v_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv8i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
+; CHECK-NEXT: vsm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1>* %1, i64 %2)
+ ret void
+}
+
+declare void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>*, i64);
+
+define void @intrinsic_vsm_v_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv16i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
+; CHECK-NEXT: vsm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1>* %1, i64 %2)
+ ret void
+}
+
+declare void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>*, i64);
+
+define void @intrinsic_vsm_v_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv32i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
+; CHECK-NEXT: vsm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1>* %1, i64 %2)
+ ret void
+}
+
+declare void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>*, i64);
+
+define void @intrinsic_vsm_v_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vsm_v_nxv64i1:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
+; CHECK-NEXT: vsm.v v0, (a0)
+; CHECK-NEXT: ret
+entry:
+ call void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1>* %1, i64 %2)
+ ret void
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
+ <vscale x 1 x i16>,
+ <vscale x 1 x i16>,
+ i64);
+
+; Make sure we can use the vsetvli from the producing instruction.
+define void @test_vsetvli_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1>* %2, i64 %3) nounwind {
+; CHECK-LABEL: test_vsetvli_i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
+; CHECK-NEXT: vmseq.vv v25, v8, v9
+; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
+ <vscale x 1 x i16> %0,
+ <vscale x 1 x i16> %1,
+ i64 %3)
+ call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i64 %3)
+ ret void
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
+ <vscale x 1 x i32>,
+ <vscale x 1 x i32>,
+ i64);
+
+define void @test_vsetvli_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1>* %2, i64 %3) nounwind {
+; CHECK-LABEL: test_vsetvli_i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
+; CHECK-NEXT: vmseq.vv v25, v8, v9
+; CHECK-NEXT: vsm.v v25, (a0)
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
+ <vscale x 1 x i32> %0,
+ <vscale x 1 x i32> %1,
+ i64 %3)
+ call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1>* %2, i64 %3)
+ ret void
+}
diff --git a/llvm/test/MC/RISCV/rvv/aliases.s b/llvm/test/MC/RISCV/rvv/aliases.s
index ba41594baa735..d6fc622de2c3e 100644
--- a/llvm/test/MC/RISCV/rvv/aliases.s
+++ b/llvm/test/MC/RISCV/rvv/aliases.s
@@ -78,3 +78,9 @@ vfneg.v v2, v1, v0.t
# ALIAS: vfabs.v v2, v1, v0.t # encoding: [0x57,0x91,0x10,0x28]
# NO-ALIAS: vfsgnjx.vv v2, v1, v1, v0.t # encoding: [0x57,0x91,0x10,0x28]
vfabs.v v2, v1, v0.t
+# ALIAS: vlm.v v8, (a0) # encoding: [0x07,0x04,0xb5,0x02]
+# NO-ALIAS: vlm.v v8, (a0) # encoding: [0x07,0x04,0xb5,0x02]
+vle1.v v8, (a0)
+# ALIAS: vsm.v v8, (a0) # encoding: [0x27,0x04,0xb5,0x02]
+# NO-ALIAS: vsm.v v8, (a0) # encoding: [0x27,0x04,0xb5,0x02]
+vse1.v v8, (a0)
diff --git a/llvm/test/MC/RISCV/rvv/load.s b/llvm/test/MC/RISCV/rvv/load.s
index 8b1c46599b7b0..42ec58b78a1d6 100644
--- a/llvm/test/MC/RISCV/rvv/load.s
+++ b/llvm/test/MC/RISCV/rvv/load.s
@@ -8,14 +8,14 @@
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-vle1.v v0, (a0)
-# CHECK-INST: vle1.v v0, (a0)
+vlm.v v0, (a0)
+# CHECK-INST: vlm.v v0, (a0)
# CHECK-ENCODING: [0x07,0x00,0xb5,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 00 b5 02 <unknown>
-vle1.v v8, (a0)
-# CHECK-INST: vle1.v v8, (a0)
+vlm.v v8, (a0)
+# CHECK-INST: vlm.v v8, (a0)
# CHECK-ENCODING: [0x07,0x04,0xb5,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 07 04 b5 02 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/store.s b/llvm/test/MC/RISCV/rvv/store.s
index e22f6b4efe838..d6e6bb0510e61 100644
--- a/llvm/test/MC/RISCV/rvv/store.s
+++ b/llvm/test/MC/RISCV/rvv/store.s
@@ -8,8 +8,8 @@
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-vse1.v v24, (a0)
-# CHECK-INST: vse1.v v24, (a0)
+vsm.v v24, (a0)
+# CHECK-INST: vsm.v v24, (a0)
# CHECK-ENCODING: [0x27,0x0c,0xb5,0x02]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 27 0c b5 02 <unknown>
More information about the llvm-commits
mailing list