[PATCH] D106044: [RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.

[Hsiangkai Wang via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG80a645630660: [RISCV] Update to vlm.v and vsm.v according to v1.0-rc1. (authored by HsiangKai).

Changed prior to commit:
  https://reviews.llvm.org/D106044?vs=359175&id=377201#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106044/new/

https://reviews.llvm.org/D106044

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
  llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
  llvm/test/CodeGen/RISCV/rvv/load-mask.ll
  llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
  llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlm-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vlm-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll
  llvm/test/MC/RISCV/rvv/aliases.s
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/store.s

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