[PATCH] D111117: [RISCV] Optimize (add (shl x, c0), c1)

[Ben Shi via Phabricator via llvm-commits]

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Transform (add (shl x, c0), c1) ->

  (add (shl (add x, c1>>c0), c0), c1-(c1>>c0<<c0)),

if c1>>c0 and c1-(c1>>c0<<c0) are simm12, while c1 is not.

Or transform (add (shl x, c0), c1) ->

  (shl (add x, c1>>c0), c0),

if c1-(c1>>c0<<c0) is zero, and c1>>c0 is simm12 while c1 is not.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111117

Files:
  llvm/test/CodeGen/RISCV/shlimm-addimm.ll

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