[llvm] bb69f1d - [test] Precommit test about hoisting invariant loads from globals
Arthur Eubanks via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 4 13:47:12 PDT 2021
Author: Arthur Eubanks
Date: 2021-10-04T13:46:47-07:00
New Revision: bb69f1dcf900f694dd5cf4af4b7212109dc26c6a
URL: https://github.com/llvm/llvm-project/commit/bb69f1dcf900f694dd5cf4af4b7212109dc26c6a
DIFF: https://github.com/llvm/llvm-project/commit/bb69f1dcf900f694dd5cf4af4b7212109dc26c6a.diff
LOG: [test] Precommit test about hoisting invariant loads from globals
And run update_test_checks.py on hoisting.ll.
Added:
Modified:
llvm/test/Transforms/LICM/hoisting.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/LICM/hoisting.ll b/llvm/test/Transforms/LICM/hoisting.ll
index 88c5b04f786d6..c77b1d62397cb 100644
--- a/llvm/test/Transforms/LICM/hoisting.ll
+++ b/llvm/test/Transforms/LICM/hoisting.ll
@@ -1,5 +1,5 @@
-; RUN: opt < %s -aa-pipeline=basic-aa -passes='require<opt-remark-emit>,loop-mssa(licm)' -S | FileCheck %s
-; RUN: opt < %s -licm -verify-memoryssa -S | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -aa-pipeline=basic-aa -passes='loop-mssa(licm)' -S | FileCheck %s
@X = global i32 0 ; <i32*> [#uses=1]
@@ -7,28 +7,42 @@ declare void @foo()
declare i32 @llvm.bitreverse.i32(i32)
-; This testcase tests for a problem where LICM hoists
+; This testcase tests for a problem where LICM hoists
; potentially trapping instructions when they are not guaranteed to execute.
define i32 @test1(i1 %c) {
; CHECK-LABEL: @test1(
- %A = load i32, i32* @X ; <i32> [#uses=2]
- br label %Loop
+; CHECK-NEXT: [[A:%.*]] = load i32, i32* @X, align 4
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: Loop:
+; CHECK-NEXT: call void @foo()
+; CHECK-NEXT: br i1 [[C:%.*]], label [[LOOPTAIL:%.*]], label [[IFUNEQUAL:%.*]]
+; CHECK: IfUnEqual:
+; CHECK-NEXT: [[B1:%.*]] = sdiv i32 4, [[A]]
+; CHECK-NEXT: br label [[LOOPTAIL]]
+; CHECK: LoopTail:
+; CHECK-NEXT: [[B:%.*]] = phi i32 [ 0, [[LOOP]] ], [ [[B1]], [[IFUNEQUAL]] ]
+; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[OUT:%.*]]
+; CHECK: Out:
+; CHECK-NEXT: [[B_LCSSA:%.*]] = phi i32 [ [[B]], [[LOOPTAIL]] ]
+; CHECK-NEXT: [[C:%.*]] = sub i32 [[A]], [[B_LCSSA]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = load i32, i32* @X ; <i32> [#uses=2]
+ br label %Loop
Loop: ; preds = %LoopTail, %0
- call void @foo( )
- br i1 %c, label %LoopTail, label %IfUnEqual
-
+ call void @foo( )
+ br i1 %c, label %LoopTail, label %IfUnEqual
+
IfUnEqual: ; preds = %Loop
-; CHECK: IfUnEqual:
-; CHECK-NEXT: sdiv i32 4, %A
- %B1 = sdiv i32 4, %A ; <i32> [#uses=1]
- br label %LoopTail
-
+ %B1 = sdiv i32 4, %A ; <i32> [#uses=1]
+ br label %LoopTail
+
LoopTail: ; preds = %IfUnEqual, %Loop
- %B = phi i32 [ 0, %Loop ], [ %B1, %IfUnEqual ] ; <i32> [#uses=1]
- br i1 %c, label %Loop, label %Out
+ %B = phi i32 [ 0, %Loop ], [ %B1, %IfUnEqual ] ; <i32> [#uses=1]
+ br i1 %c, label %Loop, label %Out
Out: ; preds = %LoopTail
- %C = sub i32 %A, %B ; <i32> [#uses=1]
- ret i32 %C
+ %C = sub i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %C
}
@@ -38,8 +52,19 @@ declare void @foo2(i32) nounwind
;; It is ok and desirable to hoist this potentially trapping instruction.
define i32 @test2(i1 %c) {
; CHECK-LABEL: @test2(
-; CHECK-NEXT: load i32, i32* @X
-; CHECK-NEXT: %B = sdiv i32 4, %A
+; CHECK-NEXT: [[A:%.*]] = load i32, i32* @X, align 4
+; CHECK-NEXT: [[B:%.*]] = sdiv i32 4, [[A]]
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: Loop:
+; CHECK-NEXT: br label [[LOOP2:%.*]]
+; CHECK: loop2:
+; CHECK-NEXT: call void @foo2(i32 [[B]])
+; CHECK-NEXT: br i1 [[C:%.*]], label [[LOOP]], label [[OUT:%.*]]
+; CHECK: Out:
+; CHECK-NEXT: [[B_LCSSA:%.*]] = phi i32 [ [[B]], [[LOOP2]] ]
+; CHECK-NEXT: [[C:%.*]] = sub i32 [[A]], [[B_LCSSA]]
+; CHECK-NEXT: ret i32 [[C]]
+;
%A = load i32, i32* @X
br label %Loop
@@ -60,24 +85,45 @@ Out:
; This loop invariant instruction should be constant folded, not hoisted.
define i32 @test3(i1 %c) {
-; CHECK-LABEL: define i32 @test3(
-; CHECK: call void @foo2(i32 6)
- %A = load i32, i32* @X ; <i32> [#uses=2]
- br label %Loop
+; CHECK-LABEL: @test3(
+; CHECK-NEXT: [[A:%.*]] = load i32, i32* @X, align 4
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: Loop:
+; CHECK-NEXT: call void @foo2(i32 6)
+; CHECK-NEXT: br i1 [[C:%.*]], label [[LOOP]], label [[OUT:%.*]]
+; CHECK: Out:
+; CHECK-NEXT: [[B_LCSSA:%.*]] = phi i32 [ 6, [[LOOP]] ]
+; CHECK-NEXT: [[C:%.*]] = sub i32 [[A]], [[B_LCSSA]]
+; CHECK-NEXT: ret i32 [[C]]
+;
+ %A = load i32, i32* @X ; <i32> [#uses=2]
+ br label %Loop
Loop:
- %B = add i32 4, 2 ; <i32> [#uses=2]
- call void @foo2( i32 %B )
- br i1 %c, label %Loop, label %Out
+ %B = add i32 4, 2 ; <i32> [#uses=2]
+ call void @foo2( i32 %B )
+ br i1 %c, label %Loop, label %Out
Out: ; preds = %Loop
- %C = sub i32 %A, %B ; <i32> [#uses=1]
- ret i32 %C
+ %C = sub i32 %A, %B ; <i32> [#uses=1]
+ ret i32 %C
}
-; CHECK-LABEL: @test4(
-; CHECK: call
-; CHECK: sdiv
-; CHECK: ret
define i32 @test4(i32 %x, i32 %y) nounwind uwtable ssp {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[I_02:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[N_01:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: call void @foo_may_call_exit(i32 0)
+; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[ADD]] = add nsw i32 [[N_01]], [[DIV]]
+; CHECK-NEXT: [[INC]] = add nsw i32 [[I_02]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[INC]], 10000
+; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]]
+; CHECK: for.end:
+; CHECK-NEXT: [[N_0_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_BODY]] ]
+; CHECK-NEXT: ret i32 [[N_0_LCSSA]]
+;
entry:
br label %for.body
@@ -99,13 +145,23 @@ for.end: ; preds = %for.body
declare void @foo_may_call_exit(i32)
; PR14854
-; CHECK-LABEL: @test5(
-; CHECK: extractvalue
-; CHECK: br label %tailrecurse
-; CHECK: tailrecurse:
-; CHECK: ifend:
-; CHECK: insertvalue
define { i32*, i32 } @test5(i32 %i, { i32*, i32 } %e) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[OUT:%.*]] = extractvalue { i32*, i32 } [[E:%.*]], 1
+; CHECK-NEXT: br label [[TAILRECURSE:%.*]]
+; CHECK: tailrecurse:
+; CHECK-NEXT: [[I_TR:%.*]] = phi i32 [ [[I:%.*]], [[ENTRY:%.*]] ], [ [[CMP2:%.*]], [[THEN:%.*]] ]
+; CHECK-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[OUT]], [[I_TR]]
+; CHECK-NEXT: br i1 [[CMP1]], label [[THEN]], label [[IFEND:%.*]]
+; CHECK: then:
+; CHECK-NEXT: call void @foo()
+; CHECK-NEXT: [[CMP2]] = add i32 [[I_TR]], 1
+; CHECK-NEXT: br label [[TAILRECURSE]]
+; CHECK: ifend:
+; CHECK-NEXT: [[D_LE:%.*]] = insertvalue { i32*, i32 } [[E]], i32* null, 0
+; CHECK-NEXT: ret { i32*, i32 } [[D_LE]]
+;
entry:
br label %tailrecurse
@@ -125,10 +181,21 @@ ifend: ; preds = %tailrecurse
ret { i32*, i32 } %d
}
-; CHECK: define void @test6(float %f)
-; CHECK: fneg
-; CHECK: br label %for.body
define void @test6(float %f) #2 {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[NEG:%.*]] = fneg float [[F:%.*]]
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: call void @foo_may_call_exit(i32 0)
+; CHECK-NEXT: call void @use(float [[NEG]])
+; CHECK-NEXT: [[INC]] = add nsw i32 [[I]], 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[INC]], 10000
+; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]]
+; CHECK: for.end:
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body
@@ -147,10 +214,25 @@ for.end: ; preds = %for.body
declare void @use(float)
-; CHECK: define i32 @hoist_bitreverse(i32 %0)
-; CHECK: bitreverse
-; CHECK: br label %header
define i32 @hoist_bitreverse(i32 %0) {
+; CHECK-LABEL: @hoist_bitreverse(
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.bitreverse.i32(i32 [[TMP0:%.*]])
+; CHECK-NEXT: br label [[HEADER:%.*]]
+; CHECK: header:
+; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, [[TMP1:%.*]] ], [ [[TMP5:%.*]], [[LATCH:%.*]] ]
+; CHECK-NEXT: [[TMP3:%.*]] = phi i32 [ 0, [[TMP1]] ], [ [[TMP6:%.*]], [[LATCH]] ]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp slt i32 [[TMP3]], 1024
+; CHECK-NEXT: br i1 [[TMP4]], label [[BODY:%.*]], label [[RETURN:%.*]]
+; CHECK: body:
+; CHECK-NEXT: [[TMP5]] = add i32 [[SUM]], [[TMP2]]
+; CHECK-NEXT: br label [[LATCH]]
+; CHECK: latch:
+; CHECK-NEXT: [[TMP6]] = add nsw i32 [[TMP3]], 1
+; CHECK-NEXT: br label [[HEADER]]
+; CHECK: return:
+; CHECK-NEXT: [[SUM_LCSSA:%.*]] = phi i32 [ [[SUM]], [[HEADER]] ]
+; CHECK-NEXT: ret i32 [[SUM_LCSSA]]
+;
br label %header
header:
@@ -175,9 +257,14 @@ return:
; Can neither sink nor hoist
define i32 @test_volatile(i1 %c) {
; CHECK-LABEL: @test_volatile(
-; CHECK-LABEL: Loop:
-; CHECK: load volatile i32, i32* @X
-; CHECK-LABEL: Out:
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: Loop:
+; CHECK-NEXT: [[A:%.*]] = load volatile i32, i32* @X, align 4
+; CHECK-NEXT: br i1 [[C:%.*]], label [[LOOP]], label [[OUT:%.*]]
+; CHECK: Out:
+; CHECK-NEXT: [[A_LCSSA:%.*]] = phi i32 [ [[A]], [[LOOP]] ]
+; CHECK-NEXT: ret i32 [[A_LCSSA]]
+;
br label %Loop
Loop:
@@ -195,12 +282,31 @@ declare void @escaping.invariant.start({}*) nounwind
; invariant.start dominates the load, and in this scope, the
; load is invariant. So, we can hoist the `addrld` load out of the loop.
define i32 @test_fence(i8* %addr, i32 %n, i8* %volatile) {
-; CHECK-LABEL: @test_fence
-; CHECK-LABEL: entry
-; CHECK: invariant.start
-; CHECK: %addrld = load atomic i32, i32* %addr.i unordered, align 8
-; CHECK: br label %loop
-entry:
+; CHECK-LABEL: @test_fence(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, i8* [[ADDR:%.*]], i64 8
+; CHECK-NEXT: [[ADDR_I:%.*]] = bitcast i8* [[GEP]] to i32*
+; CHECK-NEXT: store atomic i32 5, i32* [[ADDR_I]] unordered, align 8
+; CHECK-NEXT: fence release
+; CHECK-NEXT: [[INVST:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 4, i8* [[GEP]])
+; CHECK-NEXT: [[ADDRLD:%.*]] = load atomic i32, i32* [[ADDR_I]] unordered, align 8
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
+; CHECK-NEXT: [[VOLLOAD:%.*]] = load atomic i8, i8* [[VOLATILE:%.*]] unordered, align 8
+; CHECK-NEXT: fence acquire
+; CHECK-NEXT: [[VOLCHK:%.*]] = icmp eq i8 [[VOLLOAD]], 0
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[VOLCHK]], i32 0, i32 [[ADDRLD]]
+; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SEL]], [[SUM]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
+; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[INDVAR_NEXT]], [[N:%.*]]
+; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[LOOPEXIT:%.*]]
+; CHECK: loopexit:
+; CHECK-NEXT: [[SUM_LCSSA:%.*]] = phi i32 [ [[SUM]], [[LOOP]] ]
+; CHECK-NEXT: ret i32 [[SUM_LCSSA]]
+;
+entry:
%gep = getelementptr inbounds i8, i8* %addr, i64 8
%addr.i = bitcast i8* %gep to i32 *
store atomic i32 5, i32 * %addr.i unordered, align 8
@@ -230,11 +336,31 @@ loopexit:
; Same as test above, but the load is no longer invariant (presence of
; invariant.end). We cannot hoist the addrld out of loop.
define i32 @test_fence1(i8* %addr, i32 %n, i8* %volatile) {
-; CHECK-LABEL: @test_fence1
-; CHECK-LABEL: entry
-; CHECK: invariant.start
-; CHECK-NEXT: invariant.end
-; CHECK-NEXT: br label %loop
+; CHECK-LABEL: @test_fence1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, i8* [[ADDR:%.*]], i64 8
+; CHECK-NEXT: [[ADDR_I:%.*]] = bitcast i8* [[GEP]] to i32*
+; CHECK-NEXT: store atomic i32 5, i32* [[ADDR_I]] unordered, align 8
+; CHECK-NEXT: fence release
+; CHECK-NEXT: [[INVST:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 4, i8* [[GEP]])
+; CHECK-NEXT: call void @llvm.invariant.end.p0i8({}* [[INVST]], i64 4, i8* [[GEP]])
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
+; CHECK-NEXT: [[VOLLOAD:%.*]] = load atomic i8, i8* [[VOLATILE:%.*]] unordered, align 8
+; CHECK-NEXT: fence acquire
+; CHECK-NEXT: [[VOLCHK:%.*]] = icmp eq i8 [[VOLLOAD]], 0
+; CHECK-NEXT: [[ADDRLD:%.*]] = load atomic i32, i32* [[ADDR_I]] unordered, align 8
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[VOLCHK]], i32 0, i32 [[ADDRLD]]
+; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SEL]], [[SUM]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
+; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[INDVAR_NEXT]], [[N:%.*]]
+; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[LOOPEXIT:%.*]]
+; CHECK: loopexit:
+; CHECK-NEXT: [[SUM_LCSSA:%.*]] = phi i32 [ [[SUM]], [[LOOP]] ]
+; CHECK-NEXT: ret i32 [[SUM_LCSSA]]
+;
entry:
%gep = getelementptr inbounds i8, i8* %addr, i64 8
%addr.i = bitcast i8* %gep to i32 *
@@ -264,10 +390,31 @@ loopexit:
; same as test above, but instead of invariant.end, we have the result of
; invariant.start escaping through a call. We cannot hoist the load.
define i32 @test_fence2(i8* %addr, i32 %n, i8* %volatile) {
-; CHECK-LABEL: @test_fence2
-; CHECK-LABEL: entry
-; CHECK-NOT: load
-; CHECK: br label %loop
+; CHECK-LABEL: @test_fence2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, i8* [[ADDR:%.*]], i64 8
+; CHECK-NEXT: [[ADDR_I:%.*]] = bitcast i8* [[GEP]] to i32*
+; CHECK-NEXT: store atomic i32 5, i32* [[ADDR_I]] unordered, align 8
+; CHECK-NEXT: fence release
+; CHECK-NEXT: [[INVST:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 4, i8* [[GEP]])
+; CHECK-NEXT: call void @escaping.invariant.start({}* [[INVST]])
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
+; CHECK-NEXT: [[VOLLOAD:%.*]] = load atomic i8, i8* [[VOLATILE:%.*]] unordered, align 8
+; CHECK-NEXT: fence acquire
+; CHECK-NEXT: [[VOLCHK:%.*]] = icmp eq i8 [[VOLLOAD]], 0
+; CHECK-NEXT: [[ADDRLD:%.*]] = load atomic i32, i32* [[ADDR_I]] unordered, align 8
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[VOLCHK]], i32 0, i32 [[ADDRLD]]
+; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SEL]], [[SUM]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
+; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[INDVAR_NEXT]], [[N:%.*]]
+; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[LOOPEXIT:%.*]]
+; CHECK: loopexit:
+; CHECK-NEXT: [[SUM_LCSSA:%.*]] = phi i32 [ [[SUM]], [[LOOP]] ]
+; CHECK-NEXT: ret i32 [[SUM_LCSSA]]
+;
entry:
%gep = getelementptr inbounds i8, i8* %addr, i64 8
%addr.i = bitcast i8* %gep to i32 *
@@ -299,12 +446,31 @@ loopexit:
; Consider the loadoperand addr.i bitcasted before being passed to
; invariant.start
define i32 @test_fence3(i32* %addr, i32 %n, i8* %volatile) {
-; CHECK-LABEL: @test_fence3
-; CHECK-LABEL: entry
-; CHECK: invariant.start
-; CHECK-NOT: %addrld = load atomic i32, i32* %addr.i unordered, align 8
-; CHECK: br label %loop
-entry:
+; CHECK-LABEL: @test_fence3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ADDR_I:%.*]] = getelementptr inbounds i32, i32* [[ADDR:%.*]], i64 8
+; CHECK-NEXT: [[GEP:%.*]] = bitcast i32* [[ADDR_I]] to i8*
+; CHECK-NEXT: store atomic i32 5, i32* [[ADDR_I]] unordered, align 8
+; CHECK-NEXT: fence release
+; CHECK-NEXT: [[INVST:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 4, i8* [[GEP]])
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
+; CHECK-NEXT: [[VOLLOAD:%.*]] = load atomic i8, i8* [[VOLATILE:%.*]] unordered, align 8
+; CHECK-NEXT: fence acquire
+; CHECK-NEXT: [[VOLCHK:%.*]] = icmp eq i8 [[VOLLOAD]], 0
+; CHECK-NEXT: [[ADDRLD:%.*]] = load atomic i32, i32* [[ADDR_I]] unordered, align 8
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[VOLCHK]], i32 0, i32 [[ADDRLD]]
+; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SEL]], [[SUM]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
+; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[INDVAR_NEXT]], [[N:%.*]]
+; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[LOOPEXIT:%.*]]
+; CHECK: loopexit:
+; CHECK-NEXT: [[SUM_LCSSA:%.*]] = phi i32 [ [[SUM]], [[LOOP]] ]
+; CHECK-NEXT: ret i32 [[SUM_LCSSA]]
+;
+entry:
%addr.i = getelementptr inbounds i32, i32* %addr, i64 8
%gep = bitcast i32* %addr.i to i8 *
store atomic i32 5, i32 * %addr.i unordered, align 8
@@ -331,11 +497,31 @@ loopexit:
; We should not hoist the addrld out of the loop.
define i32 @test_fence4(i32* %addr, i32 %n, i8* %volatile) {
-; CHECK-LABEL: @test_fence4
-; CHECK-LABEL: entry
-; CHECK-NOT: %addrld = load atomic i32, i32* %addr.i unordered, align 8
-; CHECK: br label %loop
-entry:
+; CHECK-LABEL: @test_fence4(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[ADDR_I:%.*]] = getelementptr inbounds i32, i32* [[ADDR:%.*]], i64 8
+; CHECK-NEXT: [[GEP:%.*]] = bitcast i32* [[ADDR_I]] to i8*
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
+; CHECK-NEXT: store atomic i32 5, i32* [[ADDR_I]] unordered, align 8
+; CHECK-NEXT: fence release
+; CHECK-NEXT: [[INVST:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 4, i8* [[GEP]])
+; CHECK-NEXT: [[VOLLOAD:%.*]] = load atomic i8, i8* [[VOLATILE:%.*]] unordered, align 8
+; CHECK-NEXT: fence acquire
+; CHECK-NEXT: [[VOLCHK:%.*]] = icmp eq i8 [[VOLLOAD]], 0
+; CHECK-NEXT: [[ADDRLD:%.*]] = load atomic i32, i32* [[ADDR_I]] unordered, align 8
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[VOLCHK]], i32 0, i32 [[ADDRLD]]
+; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SEL]], [[SUM]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
+; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[INDVAR_NEXT]], [[N:%.*]]
+; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[LOOPEXIT:%.*]]
+; CHECK: loopexit:
+; CHECK-NEXT: [[SUM_LCSSA:%.*]] = phi i32 [ [[SUM]], [[LOOP]] ]
+; CHECK-NEXT: ret i32 [[SUM_LCSSA]]
+;
+entry:
%addr.i = getelementptr inbounds i32, i32* %addr, i64 8
%gep = bitcast i32* %addr.i to i8 *
br label %loop
@@ -363,11 +549,30 @@ loopexit:
; We can't hoist the invariant load out of the loop because
; the marker is given a variable size (-1).
define i32 @test_fence5(i8* %addr, i32 %n, i8* %volatile) {
-; CHECK-LABEL: @test_fence5
-; CHECK-LABEL: entry
-; CHECK: invariant.start
-; CHECK-NOT: %addrld = load atomic i32, i32* %addr.i unordered, align 8
-; CHECK: br label %loop
+; CHECK-LABEL: @test_fence5(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, i8* [[ADDR:%.*]], i64 8
+; CHECK-NEXT: [[ADDR_I:%.*]] = bitcast i8* [[GEP]] to i32*
+; CHECK-NEXT: store atomic i32 5, i32* [[ADDR_I]] unordered, align 8
+; CHECK-NEXT: fence release
+; CHECK-NEXT: [[INVST:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 -1, i8* [[GEP]])
+; CHECK-NEXT: br label [[LOOP:%.*]]
+; CHECK: loop:
+; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY]] ]
+; CHECK-NEXT: [[VOLLOAD:%.*]] = load atomic i8, i8* [[VOLATILE:%.*]] unordered, align 8
+; CHECK-NEXT: fence acquire
+; CHECK-NEXT: [[VOLCHK:%.*]] = icmp eq i8 [[VOLLOAD]], 0
+; CHECK-NEXT: [[ADDRLD:%.*]] = load atomic i32, i32* [[ADDR_I]] unordered, align 8
+; CHECK-NEXT: [[SEL:%.*]] = select i1 [[VOLCHK]], i32 0, i32 [[ADDRLD]]
+; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SEL]], [[SUM]]
+; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
+; CHECK-NEXT: [[COND:%.*]] = icmp slt i32 [[INDVAR_NEXT]], [[N:%.*]]
+; CHECK-NEXT: br i1 [[COND]], label [[LOOP]], label [[LOOPEXIT:%.*]]
+; CHECK: loopexit:
+; CHECK-NEXT: [[SUM_LCSSA:%.*]] = phi i32 [ [[SUM]], [[LOOP]] ]
+; CHECK-NEXT: ret i32 [[SUM_LCSSA]]
+;
entry:
%gep = getelementptr inbounds i8, i8* %addr, i64 8
%addr.i = bitcast i8* %gep to i32 *
@@ -392,3 +597,32 @@ loop:
loopexit:
ret i32 %sum
}
+
+declare void @g(i1)
+
+ at a = external global i8
+
+; FIXME: Don't hoist invariant loads of globals.
+define void @test_fence6() {
+; CHECK-LABEL: @test_fence6(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[I:%.*]] = call {}* @llvm.invariant.start.p0i8(i64 1, i8* @a)
+; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* @a, align 1
+; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[TMP0]], 0
+; CHECK-NEXT: [[T:%.*]] = icmp eq i8 [[TMP1]], 0
+; CHECK-NEXT: br label [[F:%.*]]
+; CHECK: f:
+; CHECK-NEXT: tail call void @g(i1 [[T]])
+; CHECK-NEXT: br label [[F]]
+;
+entry:
+ %i = call {}* @llvm.invariant.start.p0i8(i64 1, i8* @a)
+ br label %f
+
+f:
+ %0 = load i8, i8* @a
+ %1 = and i8 %0, 0
+ %t = icmp eq i8 %1, 0
+ tail call void @g(i1 %t)
+ br label %f
+}
More information about the llvm-commits
mailing list