[PATCH] D99142: [RISCV] Add basic cost modelling for fixed vector gather/scatter.

Mon Oct 4 08:48:58 PDT 2021

craig.topper added a comment.

In D99142#3039521 <https://reviews.llvm.org/D99142#3039521>, @luke957 wrote:

> @craig.topper It seems for intrinsic `llvm.masked.gather.xxx`, the backend will produce similar assembly instructions.  
> Eg, `llvm.masked.gather.v8f64.v8p0f64` will get
>
>   vsetivli    zero, 8, e64, m4, tu, mu
>   vluxei64.v  v12, (zero), v8, v0.t
>   vmv4r.v     v8, v12
>
> , and `llvm.masked.gather.v4f64.v4p0f64` will get
>
>   vsetivli    zero, 4, e64, m2, tu, mu
>   vluxei64.v  v10, (zero), v8, v0.t
>   vmv2r.v     v8, v10
>
> So why the cost is calculated by element number? I'm not quite clear about this. Can you give some reference or clue? Thanks.

The memory system in a chip is likely unable to handle all of the accesses in parallel since they go to disjoint addresses. Each address could be in a different cache line. Most implementations would not be able to read all of the cache lines simultaneously.

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https://reviews.llvm.org/D99142