[PATCH] D111031: [X86][Costmodel] Load/store i64/f64 Stride=3 VF=16 interleaving costs

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri updated this revision to Diff 376795.
lebedev.ri retitled this revision from "[WIP][X86][Costmodel] Load/store i64/f64 Stride=3 VF=16 interleaving costs" to "[X86][Costmodel] Load/store i64/f64 Stride=3 VF=16 interleaving costs".
lebedev.ri edited the summary of this revision.
lebedev.ri added a comment.

@RKSimon hopefully this looks right to you!
After this i think we are only missing {i32,i64}*{stride 4, stride 6}.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111031/new/

https://reviews.llvm.org/D111031

Files:
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll


Index: llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 6 for VF 2 For instruction:   store i64 %v2, i64* %out2, align 8
 ; AVX2: LV: Found an estimated cost of 9 for VF 4 For instruction:   store i64 %v2, i64* %out2, align 8
 ; AVX2: LV: Found an estimated cost of 18 for VF 8 For instruction:   store i64 %v2, i64* %out2, align 8
-; AVX2: LV: Found an estimated cost of 156 for VF 16 For instruction:   store i64 %v2, i64* %out2, align 8
+; AVX2: LV: Found an estimated cost of 36 for VF 16 For instruction:   store i64 %v2, i64* %out2, align 8
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   store i64 %v2, i64* %out2, align 8
 ; AVX512: LV: Found an estimated cost of 4 for VF 2 For instruction:   store i64 %v2, i64* %out2, align 8
Index: llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 6 for VF 2 For instruction:   store double %v2, double* %out2, align 8
 ; AVX2: LV: Found an estimated cost of 9 for VF 4 For instruction:   store double %v2, double* %out2, align 8
 ; AVX2: LV: Found an estimated cost of 18 for VF 8 For instruction:   store double %v2, double* %out2, align 8
-; AVX2: LV: Found an estimated cost of 108 for VF 16 For instruction:   store double %v2, double* %out2, align 8
+; AVX2: LV: Found an estimated cost of 36 for VF 16 For instruction:   store double %v2, double* %out2, align 8
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   store double %v2, double* %out2, align 8
 ; AVX512: LV: Found an estimated cost of 4 for VF 2 For instruction:   store double %v2, double* %out2, align 8
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 3 for VF 2 For instruction:   %v0 = load i64, i64* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 8 for VF 4 For instruction:   %v0 = load i64, i64* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 16 for VF 8 For instruction:   %v0 = load i64, i64* %in0, align 8
-; AVX2: LV: Found an estimated cost of 156 for VF 16 For instruction:   %v0 = load i64, i64* %in0, align 8
+; AVX2: LV: Found an estimated cost of 32 for VF 16 For instruction:   %v0 = load i64, i64* %in0, align 8
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load i64, i64* %in0, align 8
 ; AVX512: LV: Found an estimated cost of 4 for VF 2 For instruction:   %v0 = load i64, i64* %in0, align 8
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
@@ -27,7 +27,7 @@
 ; AVX2: LV: Found an estimated cost of 3 for VF 2 For instruction:   %v0 = load double, double* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 8 for VF 4 For instruction:   %v0 = load double, double* %in0, align 8
 ; AVX2: LV: Found an estimated cost of 16 for VF 8 For instruction:   %v0 = load double, double* %in0, align 8
-; AVX2: LV: Found an estimated cost of 96 for VF 16 For instruction:   %v0 = load double, double* %in0, align 8
+; AVX2: LV: Found an estimated cost of 32 for VF 16 For instruction:   %v0 = load double, double* %in0, align 8
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load double, double* %in0, align 8
 ; AVX512: LV: Found an estimated cost of 4 for VF 2 For instruction:   %v0 = load double, double* %in0, align 8
Index: llvm/lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -5097,6 +5097,7 @@
       {3, MVT::v2i64, 1},  // (load 6i64 and) deinterleave into 3 x 2i64
       {3, MVT::v4i64, 5},  // (load 12i64 and) deinterleave into 3 x 4i64
       {3, MVT::v8i64, 10},  // (load 24i64 and) deinterleave into 3 x 8i64
+      {3, MVT::v16i64, 20},  // (load 48i64 and) deinterleave into 3 x 16i64
 
       {4, MVT::v2i8, 4},  // (load 8i8 and) deinterleave into 4 x 2i8
       {4, MVT::v4i8, 4},   // (load 16i8 and) deinterleave into 4 x 4i8
@@ -5151,6 +5152,7 @@
       {3, MVT::v2i64, 4},   // interleave 3 x 2i64 into 6i64 (and store)
       {3, MVT::v4i64, 6},   // interleave 3 x 4i64 into 12i64 (and store)
       {3, MVT::v8i64, 12},   // interleave 3 x 8i64 into 24i64 (and store)
+      {3, MVT::v16i64, 24},   // interleave 3 x 16i64 into 48i64 (and store)
 
       {4, MVT::v2i8, 4},  // interleave 4 x 2i8 into 8i8 (and store)
       {4, MVT::v4i8, 4},   // interleave 4 x 4i8 into 16i8 (and store)


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D111031.376795.patch
Type: text/x-patch
Size: 5441 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20211003/14ef8db8/attachment.bin>