[llvm] 6fe4cce - [X86][Costmodel] Load/store i8 Stride=6 VF=4 interleaving costs
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 3 13:42:56 PDT 2021
Author: Roman Lebedev
Date: 2021-10-03T23:38:40+03:00
New Revision: 6fe4cce55816863bbb2ca9628d103dfa2d431616
URL: https://github.com/llvm/llvm-project/commit/6fe4cce55816863bbb2ca9628d103dfa2d431616
DIFF: https://github.com/llvm/llvm-project/commit/6fe4cce55816863bbb2ca9628d103dfa2d431616.diff
LOG: [X86][Costmodel] Load/store i8 Stride=6 VF=4 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/4sWhs396o - for intels `Block RThroughput: =14.0`; for ryzens, `Block RThroughput: <=7.0`
So pick cost of `14`.
For store we have:
https://godbolt.org/z/4sWhs396o - for intels `Block RThroughput: =9.0`; for ryzens, `Block RThroughput: <=3.0`
So pick cost of `9`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D111010
Added:
Modified:
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-6.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 9d4980ba487d..afbc4b0d6aac 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -5115,6 +5115,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
{4, MVT::v32i16, 150}, // (load 128i16 and) deinterleave into 4 x 32i16
{6, MVT::v2i8, 6}, // (load 12i8 and) deinterleave into 6 x 2i8
+ {6, MVT::v4i8, 14}, // (load 24i8 and) deinterleave into 6 x 4i8
{6, MVT::v2i16, 13}, // (load 12i16 and) deinterleave into 6 x 2i16
{6, MVT::v4i16, 9}, // (load 24i16 and) deinterleave into 6 x 4i16
@@ -5167,6 +5168,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
{4, MVT::v32i16, 64}, // interleave 4 x 32i16 into 128i16 (and store)
{6, MVT::v2i8, 7}, // interleave 6 x 2i8 into 12i8 (and store)
+ {6, MVT::v4i8, 9}, // interleave 6 x 4i8 into 24i8 (and store)
{6, MVT::v2i16, 10}, // interleave 6 x 2i16 into 12i16 (and store)
{6, MVT::v4i16, 15}, // interleave 6 x 4i16 into 24i16 (and store)
diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll
index ca8b9d5a411c..92023ebd302e 100644
--- a/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll
+++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll
@@ -27,7 +27,7 @@ target triple = "x86_64-unknown-linux-gnu"
;
; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i8, i8* %in0, align 1
; AVX2: LV: Found an estimated cost of 9 for VF 2 For instruction: %v0 = load i8, i8* %in0, align 1
-; AVX2: LV: Found an estimated cost of 59 for VF 4 For instruction: %v0 = load i8, i8* %in0, align 1
+; AVX2: LV: Found an estimated cost of 17 for VF 4 For instruction: %v0 = load i8, i8* %in0, align 1
; AVX2: LV: Found an estimated cost of 114 for VF 8 For instruction: %v0 = load i8, i8* %in0, align 1
; AVX2: LV: Found an estimated cost of 243 for VF 16 For instruction: %v0 = load i8, i8* %in0, align 1
; AVX2: LV: Found an estimated cost of 498 for VF 32 For instruction: %v0 = load i8, i8* %in0, align 1
diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-6.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-6.ll
index 1423fd80084f..91d3ce12a7d7 100644
--- a/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-6.ll
+++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-6.ll
@@ -27,7 +27,7 @@ target triple = "x86_64-unknown-linux-gnu"
;
; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store i8 %v5, i8* %out5, align 1
; AVX2: LV: Found an estimated cost of 10 for VF 2 For instruction: store i8 %v5, i8* %out5, align 1
-; AVX2: LV: Found an estimated cost of 54 for VF 4 For instruction: store i8 %v5, i8* %out5, align 1
+; AVX2: LV: Found an estimated cost of 12 for VF 4 For instruction: store i8 %v5, i8* %out5, align 1
; AVX2: LV: Found an estimated cost of 101 for VF 8 For instruction: store i8 %v5, i8* %out5, align 1
; AVX2: LV: Found an estimated cost of 201 for VF 16 For instruction: store i8 %v5, i8* %out5, align 1
; AVX2: LV: Found an estimated cost of 498 for VF 32 For instruction: store i8 %v5, i8* %out5, align 1
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