[PATCH] D111017: [X86][Costmodel] Load/store i16 Stride=3 VF=16 interleaving costs

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
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The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/1T6MMzeh3 - for intels `Block RThroughput: =28.0`; for ryzens, `Block RThroughput: <=8.5`
So pick cost of `28`.

For store we have:
https://godbolt.org/z/1T6MMzeh3 - for intels `Block RThroughput: <=27.0`; for ryzens, `Block RThroughput: <=7.0`
So pick cost of `27`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111017

Files:
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll


Index: llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll
@@ -29,7 +29,7 @@
 ; AVX2: LV: Found an estimated cost of 7 for VF 2 For instruction:   store i16 %v2, i16* %out2, align 2
 ; AVX2: LV: Found an estimated cost of 9 for VF 4 For instruction:   store i16 %v2, i16* %out2, align 2
 ; AVX2: LV: Found an estimated cost of 14 for VF 8 For instruction:   store i16 %v2, i16* %out2, align 2
-; AVX2: LV: Found an estimated cost of 129 for VF 16 For instruction:   store i16 %v2, i16* %out2, align 2
+; AVX2: LV: Found an estimated cost of 30 for VF 16 For instruction:   store i16 %v2, i16* %out2, align 2
 ; AVX2: LV: Found an estimated cost of 258 for VF 32 For instruction:   store i16 %v2, i16* %out2, align 2
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   store i16 %v2, i16* %out2, align 2
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
@@ -29,7 +29,7 @@
 ; AVX2: LV: Found an estimated cost of 8 for VF 2 For instruction:   %v0 = load i16, i16* %in0, align 2
 ; AVX2: LV: Found an estimated cost of 10 for VF 4 For instruction:   %v0 = load i16, i16* %in0, align 2
 ; AVX2: LV: Found an estimated cost of 11 for VF 8 For instruction:   %v0 = load i16, i16* %in0, align 2
-; AVX2: LV: Found an estimated cost of 129 for VF 16 For instruction:   %v0 = load i16, i16* %in0, align 2
+; AVX2: LV: Found an estimated cost of 31 for VF 16 For instruction:   %v0 = load i16, i16* %in0, align 2
 ; AVX2: LV: Found an estimated cost of 258 for VF 32 For instruction:   %v0 = load i16, i16* %in0, align 2
 ;
 ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load i16, i16* %in0, align 2
Index: llvm/lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -5095,6 +5095,7 @@
       {3, MVT::v2i16, 5},  // (load 6i16 and) deinterleave into 3 x 2i16
       {3, MVT::v4i16, 7},  // (load 12i16 and) deinterleave into 3 x 4i16
       {3, MVT::v8i16, 9},  // (load 24i16 and) deinterleave into 3 x 8i16
+      {3, MVT::v16i16, 28},  // (load 48i16 and) deinterleave into 3 x 16i16
 
       {3, MVT::v8i32, 17}, // (load 24i32 and) deinterleave into 3 x 8i32
 
@@ -5151,6 +5152,7 @@
       {3, MVT::v2i16, 4},   // interleave 3 x 2i16 into 6i16 (and store)
       {3, MVT::v4i16, 6},   // interleave 3 x 4i16 into 12i16 (and store)
       {3, MVT::v8i16, 12},   // interleave 3 x 8i16 into 24i16 (and store)
+      {3, MVT::v16i16, 27},   // interleave 3 x 16i16 into 48i16 (and store)
 
       {4, MVT::v2i8, 4},  // interleave 4 x 2i8 into 8i8 (and store)
       {4, MVT::v4i8, 4},   // interleave 4 x 4i8 into 16i8 (and store)


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