[llvm] fd8e997 - [DetectDeadLanes] Enable machine verification after this pass
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 1 10:16:10 PDT 2021
Author: Jay Foad
Date: 2021-10-01T18:15:56+01:00
New Revision: fd8e99700de6b769c76bef9e580b712fee22205d
URL: https://github.com/llvm/llvm-project/commit/fd8e99700de6b769c76bef9e580b712fee22205d
DIFF: https://github.com/llvm/llvm-project/commit/fd8e99700de6b769c76bef9e580b712fee22205d.diff
LOG: [DetectDeadLanes] Enable machine verification after this pass
Machine verification after DetectDeadLanes has been disabled since the
pass was first added in D18427, but I guess this was just due to copy-
and-paste. Enabling it does not show any problems in check-llvm in an
LLVM_ENABLE_EXPENSIVE_CHECKS build.
Differential Revision: https://reviews.llvm.org/D110689
Added:
Modified:
llvm/lib/CodeGen/TargetPassConfig.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 0d9f2b2b8651..16a7a15a7cab 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -1427,7 +1427,7 @@ void TargetPassConfig::addFastRegAlloc() {
/// optimized register allocation, including coalescing, machine instruction
/// scheduling, and register allocation itself.
void TargetPassConfig::addOptimizedRegAlloc() {
- addPass(&DetectDeadLanesID, false);
+ addPass(&DetectDeadLanesID);
addPass(&ProcessImplicitDefsID, false);
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