[llvm] 3a0643e - [X86][Costmodel] Load/store i32/f32 Stride=2 VF=8 interleaving costs
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 1 07:49:13 PDT 2021
Author: Roman Lebedev
Date: 2021-10-01T17:48:13+03:00
New Revision: 3a0643e9c2252290a9f29c2b3ceb696033af4903
URL: https://github.com/llvm/llvm-project/commit/3a0643e9c2252290a9f29c2b3ceb696033af4903
DIFF: https://github.com/llvm/llvm-project/commit/3a0643e9c2252290a9f29c2b3ceb696033af4903.diff
LOG: [X86][Costmodel] Load/store i32/f32 Stride=2 VF=8 interleaving costs
The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3
For load we have:
https://godbolt.org/z/n8aMKeo4E - for intels `Block RThroughput: =4.0`; for ryzens, `Block RThroughput: <=2.0`
So pick cost of `4`.
For store we have:
https://godbolt.org/z/n8aMKeo4E - for intels `Block RThroughput: =4.0`; for ryzens, `Block RThroughput: =2.0`
So pick cost of `4`.
I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D110755
Added:
Modified:
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll
llvm/test/Transforms/LoopVectorize/X86/interleaving.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index 36e6cf436b18c..8bfdb614a3a10 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -5077,6 +5077,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
{2, MVT::v2i32, 2}, // (load 4i32 and) deinterleave into 2 x 2i32
{2, MVT::v4i32, 2}, // (load 8i32 and) deinterleave into 2 x 4i32
+ {2, MVT::v8i32, 4}, // (load 16i32 and) deinterleave into 2 x 8i32
{2, MVT::v4i64, 6}, // (load 8i64 and) deinterleave into 2 x 4i64
@@ -5123,6 +5124,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2(
{2, MVT::v2i32, 1}, // interleave 2 x 2i32 into 4i32 (and store)
{2, MVT::v4i32, 2}, // interleave 2 x 4i32 into 8i32 (and store)
+ {2, MVT::v8i32, 4}, // interleave 2 x 8i32 into 16i32 (and store)
{2, MVT::v4i64, 6}, // interleave 2 x 4i64 into 8i64 (and store)
diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
index 369dbe70045e5..34e51047120bd 100644
--- a/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
+++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
@@ -28,7 +28,7 @@ target triple = "x86_64-unknown-linux-gnu"
; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load float, float* %in0, align 4
; AVX2: LV: Found an estimated cost of 3 for VF 2 For instruction: %v0 = load float, float* %in0, align 4
; AVX2: LV: Found an estimated cost of 3 for VF 4 For instruction: %v0 = load float, float* %in0, align 4
-; AVX2: LV: Found an estimated cost of 38 for VF 8 For instruction: %v0 = load float, float* %in0, align 4
+; AVX2: LV: Found an estimated cost of 6 for VF 8 For instruction: %v0 = load float, float* %in0, align 4
; AVX2: LV: Found an estimated cost of 76 for VF 16 For instruction: %v0 = load float, float* %in0, align 4
; AVX2: LV: Found an estimated cost of 152 for VF 32 For instruction: %v0 = load float, float* %in0, align 4
;
diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
index 6e07222d90f20..339b06dafc353 100644
--- a/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
+++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
@@ -28,7 +28,7 @@ target triple = "x86_64-unknown-linux-gnu"
; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i32, i32* %in0, align 4
; AVX2: LV: Found an estimated cost of 3 for VF 2 For instruction: %v0 = load i32, i32* %in0, align 4
; AVX2: LV: Found an estimated cost of 3 for VF 4 For instruction: %v0 = load i32, i32* %in0, align 4
-; AVX2: LV: Found an estimated cost of 46 for VF 8 For instruction: %v0 = load i32, i32* %in0, align 4
+; AVX2: LV: Found an estimated cost of 6 for VF 8 For instruction: %v0 = load i32, i32* %in0, align 4
; AVX2: LV: Found an estimated cost of 92 for VF 16 For instruction: %v0 = load i32, i32* %in0, align 4
; AVX2: LV: Found an estimated cost of 184 for VF 32 For instruction: %v0 = load i32, i32* %in0, align 4
;
diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll
index 0998cab6f1a6c..cb01b28e38b19 100644
--- a/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll
+++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll
@@ -28,7 +28,7 @@ target triple = "x86_64-unknown-linux-gnu"
; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store float %v1, float* %out1, align 4
; AVX2: LV: Found an estimated cost of 2 for VF 2 For instruction: store float %v1, float* %out1, align 4
; AVX2: LV: Found an estimated cost of 3 for VF 4 For instruction: store float %v1, float* %out1, align 4
-; AVX2: LV: Found an estimated cost of 38 for VF 8 For instruction: store float %v1, float* %out1, align 4
+; AVX2: LV: Found an estimated cost of 6 for VF 8 For instruction: store float %v1, float* %out1, align 4
; AVX2: LV: Found an estimated cost of 76 for VF 16 For instruction: store float %v1, float* %out1, align 4
; AVX2: LV: Found an estimated cost of 152 for VF 32 For instruction: store float %v1, float* %out1, align 4
;
diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll
index 5dc4cce71794d..a26792fa8bc40 100644
--- a/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll
+++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll
@@ -28,7 +28,7 @@ target triple = "x86_64-unknown-linux-gnu"
; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store i32 %v1, i32* %out1, align 4
; AVX2: LV: Found an estimated cost of 2 for VF 2 For instruction: store i32 %v1, i32* %out1, align 4
; AVX2: LV: Found an estimated cost of 3 for VF 4 For instruction: store i32 %v1, i32* %out1, align 4
-; AVX2: LV: Found an estimated cost of 46 for VF 8 For instruction: store i32 %v1, i32* %out1, align 4
+; AVX2: LV: Found an estimated cost of 6 for VF 8 For instruction: store i32 %v1, i32* %out1, align 4
; AVX2: LV: Found an estimated cost of 92 for VF 16 For instruction: store i32 %v1, i32* %out1, align 4
; AVX2: LV: Found an estimated cost of 184 for VF 32 For instruction: store i32 %v1, i32* %out1, align 4
;
diff --git a/llvm/test/Transforms/LoopVectorize/X86/interleaving.ll b/llvm/test/Transforms/LoopVectorize/X86/interleaving.ll
index d37ab074ae9dd..d609e19d945a1 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/interleaving.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/interleaving.ll
@@ -64,48 +64,48 @@ define void @foo(i32* noalias nocapture %a, i32* noalias nocapture readonly %b)
; AVX2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; AVX2-NEXT: [[TMP0:%.*]] = shl nsw i64 [[INDEX]], 1
; AVX2-NEXT: [[TMP1:%.*]] = shl i64 [[INDEX]], 1
-; AVX2-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 8
+; AVX2-NEXT: [[TMP2:%.*]] = or i64 [[TMP1]], 16
; AVX2-NEXT: [[TMP3:%.*]] = shl i64 [[INDEX]], 1
-; AVX2-NEXT: [[TMP4:%.*]] = or i64 [[TMP3]], 16
+; AVX2-NEXT: [[TMP4:%.*]] = or i64 [[TMP3]], 32
; AVX2-NEXT: [[TMP5:%.*]] = shl i64 [[INDEX]], 1
-; AVX2-NEXT: [[TMP6:%.*]] = or i64 [[TMP5]], 24
+; AVX2-NEXT: [[TMP6:%.*]] = or i64 [[TMP5]], 48
; AVX2-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i64 [[TMP0]]
; AVX2-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[TMP2]]
; AVX2-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[TMP4]]
; AVX2-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 [[TMP6]]
-; AVX2-NEXT: [[TMP11:%.*]] = bitcast i32* [[TMP7]] to <8 x i32>*
-; AVX2-NEXT: [[TMP12:%.*]] = bitcast i32* [[TMP8]] to <8 x i32>*
-; AVX2-NEXT: [[TMP13:%.*]] = bitcast i32* [[TMP9]] to <8 x i32>*
-; AVX2-NEXT: [[TMP14:%.*]] = bitcast i32* [[TMP10]] to <8 x i32>*
-; AVX2-NEXT: [[WIDE_VEC:%.*]] = load <8 x i32>, <8 x i32>* [[TMP11]], align 4
-; AVX2-NEXT: [[WIDE_VEC1:%.*]] = load <8 x i32>, <8 x i32>* [[TMP12]], align 4
-; AVX2-NEXT: [[WIDE_VEC2:%.*]] = load <8 x i32>, <8 x i32>* [[TMP13]], align 4
-; AVX2-NEXT: [[WIDE_VEC3:%.*]] = load <8 x i32>, <8 x i32>* [[TMP14]], align 4
-; AVX2-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
-; AVX2-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <8 x i32> [[WIDE_VEC1]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
-; AVX2-NEXT: [[STRIDED_VEC5:%.*]] = shufflevector <8 x i32> [[WIDE_VEC2]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
-; AVX2-NEXT: [[STRIDED_VEC6:%.*]] = shufflevector <8 x i32> [[WIDE_VEC3]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
-; AVX2-NEXT: [[STRIDED_VEC7:%.*]] = shufflevector <8 x i32> [[WIDE_VEC]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
-; AVX2-NEXT: [[STRIDED_VEC8:%.*]] = shufflevector <8 x i32> [[WIDE_VEC1]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
-; AVX2-NEXT: [[STRIDED_VEC9:%.*]] = shufflevector <8 x i32> [[WIDE_VEC2]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
-; AVX2-NEXT: [[STRIDED_VEC10:%.*]] = shufflevector <8 x i32> [[WIDE_VEC3]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
-; AVX2-NEXT: [[TMP15:%.*]] = add nsw <4 x i32> [[STRIDED_VEC7]], [[STRIDED_VEC]]
-; AVX2-NEXT: [[TMP16:%.*]] = add nsw <4 x i32> [[STRIDED_VEC8]], [[STRIDED_VEC4]]
-; AVX2-NEXT: [[TMP17:%.*]] = add nsw <4 x i32> [[STRIDED_VEC9]], [[STRIDED_VEC5]]
-; AVX2-NEXT: [[TMP18:%.*]] = add nsw <4 x i32> [[STRIDED_VEC10]], [[STRIDED_VEC6]]
+; AVX2-NEXT: [[TMP11:%.*]] = bitcast i32* [[TMP7]] to <16 x i32>*
+; AVX2-NEXT: [[TMP12:%.*]] = bitcast i32* [[TMP8]] to <16 x i32>*
+; AVX2-NEXT: [[TMP13:%.*]] = bitcast i32* [[TMP9]] to <16 x i32>*
+; AVX2-NEXT: [[TMP14:%.*]] = bitcast i32* [[TMP10]] to <16 x i32>*
+; AVX2-NEXT: [[WIDE_VEC:%.*]] = load <16 x i32>, <16 x i32>* [[TMP11]], align 4
+; AVX2-NEXT: [[WIDE_VEC1:%.*]] = load <16 x i32>, <16 x i32>* [[TMP12]], align 4
+; AVX2-NEXT: [[WIDE_VEC2:%.*]] = load <16 x i32>, <16 x i32>* [[TMP13]], align 4
+; AVX2-NEXT: [[WIDE_VEC3:%.*]] = load <16 x i32>, <16 x i32>* [[TMP14]], align 4
+; AVX2-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <16 x i32> [[WIDE_VEC]], <16 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+; AVX2-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <16 x i32> [[WIDE_VEC1]], <16 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+; AVX2-NEXT: [[STRIDED_VEC5:%.*]] = shufflevector <16 x i32> [[WIDE_VEC2]], <16 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+; AVX2-NEXT: [[STRIDED_VEC6:%.*]] = shufflevector <16 x i32> [[WIDE_VEC3]], <16 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+; AVX2-NEXT: [[STRIDED_VEC7:%.*]] = shufflevector <16 x i32> [[WIDE_VEC]], <16 x i32> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+; AVX2-NEXT: [[STRIDED_VEC8:%.*]] = shufflevector <16 x i32> [[WIDE_VEC1]], <16 x i32> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+; AVX2-NEXT: [[STRIDED_VEC9:%.*]] = shufflevector <16 x i32> [[WIDE_VEC2]], <16 x i32> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+; AVX2-NEXT: [[STRIDED_VEC10:%.*]] = shufflevector <16 x i32> [[WIDE_VEC3]], <16 x i32> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+; AVX2-NEXT: [[TMP15:%.*]] = add nsw <8 x i32> [[STRIDED_VEC7]], [[STRIDED_VEC]]
+; AVX2-NEXT: [[TMP16:%.*]] = add nsw <8 x i32> [[STRIDED_VEC8]], [[STRIDED_VEC4]]
+; AVX2-NEXT: [[TMP17:%.*]] = add nsw <8 x i32> [[STRIDED_VEC9]], [[STRIDED_VEC5]]
+; AVX2-NEXT: [[TMP18:%.*]] = add nsw <8 x i32> [[STRIDED_VEC10]], [[STRIDED_VEC6]]
; AVX2-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[INDEX]]
-; AVX2-NEXT: [[TMP20:%.*]] = bitcast i32* [[TMP19]] to <4 x i32>*
-; AVX2-NEXT: store <4 x i32> [[TMP15]], <4 x i32>* [[TMP20]], align 4
-; AVX2-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 4
-; AVX2-NEXT: [[TMP22:%.*]] = bitcast i32* [[TMP21]] to <4 x i32>*
-; AVX2-NEXT: store <4 x i32> [[TMP16]], <4 x i32>* [[TMP22]], align 4
-; AVX2-NEXT: [[TMP23:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 8
-; AVX2-NEXT: [[TMP24:%.*]] = bitcast i32* [[TMP23]] to <4 x i32>*
-; AVX2-NEXT: store <4 x i32> [[TMP17]], <4 x i32>* [[TMP24]], align 4
-; AVX2-NEXT: [[TMP25:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 12
-; AVX2-NEXT: [[TMP26:%.*]] = bitcast i32* [[TMP25]] to <4 x i32>*
-; AVX2-NEXT: store <4 x i32> [[TMP18]], <4 x i32>* [[TMP26]], align 4
-; AVX2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
+; AVX2-NEXT: [[TMP20:%.*]] = bitcast i32* [[TMP19]] to <8 x i32>*
+; AVX2-NEXT: store <8 x i32> [[TMP15]], <8 x i32>* [[TMP20]], align 4
+; AVX2-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 8
+; AVX2-NEXT: [[TMP22:%.*]] = bitcast i32* [[TMP21]] to <8 x i32>*
+; AVX2-NEXT: store <8 x i32> [[TMP16]], <8 x i32>* [[TMP22]], align 4
+; AVX2-NEXT: [[TMP23:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 16
+; AVX2-NEXT: [[TMP24:%.*]] = bitcast i32* [[TMP23]] to <8 x i32>*
+; AVX2-NEXT: store <8 x i32> [[TMP17]], <8 x i32>* [[TMP24]], align 4
+; AVX2-NEXT: [[TMP25:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 24
+; AVX2-NEXT: [[TMP26:%.*]] = bitcast i32* [[TMP25]] to <8 x i32>*
+; AVX2-NEXT: store <8 x i32> [[TMP18]], <8 x i32>* [[TMP26]], align 4
+; AVX2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32
; AVX2-NEXT: [[TMP27:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
; AVX2-NEXT: br i1 [[TMP27]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; AVX2: middle.block:
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