[PATCH] D110841: [AArch64] Remove redundant ORRWrs which is generated by zero-extend

JinGu Kang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Oct 1 03:47:36 PDT 2021


jaykang10 updated this revision to Diff 376464.
jaykang10 added a comment.

Fixed a bug

- `replaceRegWith` changes MI's defintion register. Keep it for SSA form until deleting MI.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110841/new/

https://reviews.llvm.org/D110841

Files:
  llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
  llvm/test/CodeGen/AArch64/redundant-mov-from-zero-extend.ll

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