[llvm] a21c557 - [RISCV] Remove Zbproposedc extension
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 30 14:23:13 PDT 2021
Author: Craig Topper
Date: 2021-09-30T14:23:05-07:00
New Revision: a21c557955c6ea5cd02b9a145ad6469c608446c7
URL: https://github.com/llvm/llvm-project/commit/a21c557955c6ea5cd02b9a145ad6469c608446c7
DIFF: https://github.com/llvm/llvm-project/commit/a21c557955c6ea5cd02b9a145ad6469c608446c7.diff
LOG: [RISCV] Remove Zbproposedc extension
This consists of 3 compressed instructions, c.not, c.neg, and c.zext.w.
I believe these have been picked up by the Zce effort using different
encodings. I don't think it makes sense to keep them in bitmanip. It
will eventually cause a conflict if/when Zce is implemented in llvm.
Differential Revision: https://reviews.llvm.org/D110871
Added:
Modified:
clang/lib/Basic/Targets/RISCV.cpp
clang/lib/Basic/Targets/RISCV.h
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
Removed:
llvm/test/MC/RISCV/compress-rv32b.s
llvm/test/MC/RISCV/compress-rv64b.s
llvm/test/MC/RISCV/rv32zbproposedc-invalid.s
llvm/test/MC/RISCV/rv32zbproposedc-valid.s
llvm/test/MC/RISCV/rv64zbproposedc-invalid.s
llvm/test/MC/RISCV/rv64zbproposedc-valid.s
################################################################################
diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
index 567f600871352..88de246f7bd7c 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -207,9 +207,6 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
if (HasZbp)
Builder.defineMacro("__riscv_zbp", "93000");
- if (HasZbproposedc)
- Builder.defineMacro("__riscv_zbproposedc", "93000");
-
if (HasZbr)
Builder.defineMacro("__riscv_zbr", "93000");
@@ -274,7 +271,6 @@ bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
.Case("experimental-zbf", HasZbf)
.Case("experimental-zbm", HasZbm)
.Case("experimental-zbp", HasZbp)
- .Case("experimental-zbproposedc", HasZbproposedc)
.Case("experimental-zbr", HasZbr)
.Case("experimental-zbs", HasZbs)
.Case("experimental-zbt", HasZbt)
@@ -316,8 +312,6 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasZbm = true;
else if (Feature == "+experimental-zbp")
HasZbp = true;
- else if (Feature == "+experimental-zbproposedc")
- HasZbproposedc = true;
else if (Feature == "+experimental-zbr")
HasZbr = true;
else if (Feature == "+experimental-zbs")
diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h
index 9609b6fc3f307..a26a9a41176e8 100644
--- a/clang/lib/Basic/Targets/RISCV.h
+++ b/clang/lib/Basic/Targets/RISCV.h
@@ -39,7 +39,6 @@ class RISCVTargetInfo : public TargetInfo {
bool HasZbf = false;
bool HasZbm = false;
bool HasZbp = false;
- bool HasZbproposedc = false;
bool HasZbr = false;
bool HasZbs = false;
bool HasZbt = false;
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index ade93d6881a7a..3e724d69b897c 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -60,7 +60,7 @@ static Optional<RISCVExtensionVersion>
isExperimentalExtension(StringRef Ext) {
if (Ext == "b" || Ext == "zba" || Ext == "zbb" || Ext == "zbc" ||
Ext == "zbe" || Ext == "zbf" || Ext == "zbm" || Ext == "zbp" ||
- Ext == "zbr" || Ext == "zbs" || Ext == "zbt" || Ext == "zbproposedc")
+ Ext == "zbr" || Ext == "zbs" || Ext == "zbt")
return RISCVExtensionVersion{"0", "93"};
if (Ext == "v" || Ext == "zvamo" || Ext == "zvlsseg")
return RISCVExtensionVersion{"0", "10"};
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index ea5754a83f1ea..bc6cbd24eb869 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -25,7 +25,6 @@
// CHECK-NOT: __riscv_zbf
// CHECK-NOT: __riscv_zbm
// CHECK-NOT: __riscv_zbp
-// CHECK-NOT: __riscv_zbproposedc
// CHECK-NOT: __riscv_zbr
// CHECK-NOT: __riscv_zbs
// CHECK-NOT: __riscv_zbt
@@ -182,15 +181,6 @@
// CHECK-ZBP-NOT: __riscv_b
// CHECK-ZBP-EXT: __riscv_zbp 93000
-// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv32izbproposedc0p93 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZBPROPOSEDC-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
-// RUN: -march=rv32izbproposedc0p93 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZBPROPOSEDC-EXT %s
-// CHECK-ZBPROPOSEDC-NOT: __riscv_b
-// CHECK-ZBPROPOSEDC-EXT: __riscv_zbproposedc 93000
-
// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
// RUN: -march=rv32izbr0p93 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZBR-EXT %s
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 4aded1800173f..f798d53e4e44b 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2078,8 +2078,6 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
clearFeatureBits(RISCV::FeatureStdExtZbf, "experimental-zbf");
clearFeatureBits(RISCV::FeatureStdExtZbm, "experimental-zbm");
clearFeatureBits(RISCV::FeatureStdExtZbp, "experimental-zbp");
- clearFeatureBits(RISCV::FeatureStdExtZbproposedc,
- "experimental-zbproposedc");
clearFeatureBits(RISCV::FeatureStdExtZbr, "experimental-zbr");
clearFeatureBits(RISCV::FeatureStdExtZbs, "experimental-zbs");
clearFeatureBits(RISCV::FeatureStdExtZbt, "experimental-zbt");
@@ -2130,9 +2128,6 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
setFeatureBits(RISCV::FeatureStdExtZbm, "experimental-zbm");
else if (Ext == "zbp")
setFeatureBits(RISCV::FeatureStdExtZbp, "experimental-zbp");
- else if (Ext == "zbproposedc")
- setFeatureBits(RISCV::FeatureStdExtZbproposedc,
- "experimental-zbproposedc");
else if (Ext == "zbr")
setFeatureBits(RISCV::FeatureStdExtZbr, "experimental-zbr");
else if (Ext == "zbs")
@@ -2207,8 +2202,6 @@ bool RISCVAsmParser::parseDirectiveAttribute() {
formalArchStr = (Twine(formalArchStr) + "_zbm0p93").str();
if (getFeatureBits(RISCV::FeatureStdExtZbp))
formalArchStr = (Twine(formalArchStr) + "_zbp0p93").str();
- if (getFeatureBits(RISCV::FeatureStdExtZbproposedc))
- formalArchStr = (Twine(formalArchStr) + "_zbproposedc0p93").str();
if (getFeatureBits(RISCV::FeatureStdExtZbr))
formalArchStr = (Twine(formalArchStr) + "_zbr0p93").str();
if (getFeatureBits(RISCV::FeatureStdExtZbs))
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index d5cdac569d79c..4bfb00670b7c1 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -449,19 +449,6 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
}
}
- if (STI.getFeatureBits()[RISCV::FeatureStdExtZbproposedc] &&
- STI.getFeatureBits()[RISCV::FeatureStdExtC]) {
- LLVM_DEBUG(
- dbgs() << "Trying RVBC32 table (BitManip 16-bit Instruction):\n");
- // Calling the auto-generated decoder function.
- Result = decodeInstruction(DecoderTableRVBC16, MI, Insn, Address,
- this, STI);
- if (Result != MCDisassembler::Fail) {
- Size = 2;
- return Result;
- }
- }
-
LLVM_DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
// Calling the auto-generated decoder function.
Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index fd6e49d02c22f..3b69c5ee91833 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -80,8 +80,6 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
Arch += "_zbm0p93";
if (STI.hasFeature(RISCV::FeatureStdExtZbp))
Arch += "_zbp0p93";
- if (STI.hasFeature(RISCV::FeatureStdExtZbproposedc))
- Arch += "_zbproposedc0p93";
if (STI.hasFeature(RISCV::FeatureStdExtZbr))
Arch += "_zbr0p93";
if (STI.hasFeature(RISCV::FeatureStdExtZbs))
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index ae6c6b252d22d..fdb97fe49f48d 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -135,13 +135,6 @@ def HasStdExtZbbOrZbp
"'Zbb' (Base 'B' Instructions) or "
"'Zbp' (Permutation 'B' Instructions)">;
-def FeatureStdExtZbproposedc
- : SubtargetFeature<"experimental-zbproposedc", "HasStdExtZbproposedc", "true",
- "'Zbproposedc' (Proposed Compressed 'B' Instructions)">;
-def HasStdExtZbproposedc : Predicate<"Subtarget->hasStdExtZbproposedc()">,
- AssemblerPredicate<(all_of FeatureStdExtZbproposedc),
- "'Zbproposedc' (Proposed Compressed 'B' Instructions)">;
-
def FeatureStdExtB
: SubtargetFeature<"experimental-b", "HasStdExtB", "true",
"'B' (Bit Manipulation Instructions)",
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index d2e77ae86a83c..fb7075a4374b2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -610,37 +610,6 @@ def ORCB : RVInstI<0b101, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1),
}
} // Predicates = [HasStdExtZbbOrZbp]
-//===----------------------------------------------------------------------===//
-// Future compressed instructions
-//===----------------------------------------------------------------------===//
-
-// The presence of these instructions in the B extension is purely experimental
-// and they should be moved to the C extension as soon as they are ratified.
-
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class RVBInstC<bits<2> funct2, string opcodestr>
- : RVInst16<(outs GPRC:$rs_wb), (ins GPRC:$rs), opcodestr, "$rs", [],
- InstFormatCR> {
- bits<3> rs;
- let Constraints = "$rs = $rs_wb";
-
- let Inst{15-12} = 0b0110;
- let Inst{11-10} = funct2;
- let Inst{9-7} = rs;
- let Inst{6-0} = 0b0000001;
-}
-
-// The namespace RVBC exists to avoid encoding conflicts with the compressed
-// instructions c.addi16sp and c.lui already implemented in the C extension.
-
-let DecoderNamespace = "RVBC", Predicates = [HasStdExtZbproposedc, HasStdExtC] in {
-def C_NOT : RVBInstC<0b00, "c.not">, Sched<[]>;
-def C_NEG : RVBInstC<0b01, "c.neg">, Sched<[]>;
-} // DecoderNamespace = "RVBC", Predicates = [HasStdExtZbproposedc, HasStdExtC]
-
-let DecoderNamespace = "RVBC", Predicates = [HasStdExtZbproposedc, HasStdExtZba, HasStdExtC, IsRV64] in
-def C_ZEXTW : RVBInstC<0b10, "c.zext.w">, Sched<[]>;
-
//===----------------------------------------------------------------------===//
// Pseudo Instructions
//===----------------------------------------------------------------------===//
@@ -795,21 +764,6 @@ def : InstAlias<"bext $rd, $rs1, $shamt",
(BEXTI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
} // Predicates = [HasStdExtZbs]
-//===----------------------------------------------------------------------===//
-// Compressed Instruction patterns
-//===----------------------------------------------------------------------===//
-let Predicates = [HasStdExtZbproposedc, HasStdExtC] in {
-def : CompressPat<(XORI GPRC:$rs1, GPRC:$rs1, -1),
- (C_NOT GPRC:$rs1)>;
-def : CompressPat<(SUB GPRC:$rs1, X0, GPRC:$rs1),
- (C_NEG GPRC:$rs1)>;
-} // Predicates = [HasStdExtZbproposedc, HasStdExtC]
-
-let Predicates = [HasStdExtZbproposedc, HasStdExtZba, HasStdExtC, IsRV64] in {
-def : CompressPat<(ADDUW GPRC:$rs1, GPRC:$rs1, X0),
- (C_ZEXTW GPRC:$rs1)>;
-} // Predicates = [HasStdExtZbproposedc, HasStdExtC, IsRV64]
-
//===----------------------------------------------------------------------===//
// Codegen patterns
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index cf33ebf8cc514..6075c7813f875 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -50,7 +50,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool HasStdExtZbr = false;
bool HasStdExtZbs = false;
bool HasStdExtZbt = false;
- bool HasStdExtZbproposedc = false;
bool HasStdExtV = false;
bool HasStdExtZvlsseg = false;
bool HasStdExtZvamo = false;
@@ -118,7 +117,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool hasStdExtZbr() const { return HasStdExtZbr; }
bool hasStdExtZbs() const { return HasStdExtZbs; }
bool hasStdExtZbt() const { return HasStdExtZbt; }
- bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
bool hasStdExtV() const { return HasStdExtV; }
bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
bool hasStdExtZvamo() const { return HasStdExtZvamo; }
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index c26a6d5b4a69c..db0ed8b0964d5 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -15,7 +15,6 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV32ZBF %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV32ZBM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV32ZBP %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbproposedc %s -o - | FileCheck --check-prefix=RV32ZBPROPOSEDC %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
@@ -35,7 +34,6 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbf %s -o - | FileCheck --check-prefix=RV64ZBF %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbm %s -o - | FileCheck --check-prefix=RV64ZBM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbp %s -o - | FileCheck --check-prefix=RV64ZBP %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbproposedc %s -o - | FileCheck --check-prefix=RV64ZBPROPOSEDC %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
@@ -56,7 +54,6 @@
; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93"
; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93"
; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93"
-; RV32ZBPROPOSEDC: .attribute 5, "rv32i2p0_zbproposedc0p93"
; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
@@ -76,7 +73,6 @@
; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93"
; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93"
; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93"
-; RV64ZBPROPOSEDC: .attribute 5, "rv64i2p0_zbproposedc0p93"
; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
; RV64ZBS: .attribute 5, "rv64i2p0_zbs0p93"
; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 51d0c6ace9e19..e4f1b25f42b66 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -63,9 +63,6 @@
.attribute arch, "rv32izbp"
# CHECK: attribute 5, "rv32i2p0_zbp0p93"
-.attribute arch, "rv32izbproposedc"
-# CHECK: attribute 5, "rv32i2p0_zbproposedc0p93"
-
.attribute arch, "rv32izbr"
# CHECK: attribute 5, "rv32i2p0_zbr0p93"
diff --git a/llvm/test/MC/RISCV/compress-rv32b.s b/llvm/test/MC/RISCV/compress-rv32b.s
deleted file mode 100644
index 339ae5c2d0343..0000000000000
--- a/llvm/test/MC/RISCV/compress-rv32b.s
+++ /dev/null
@@ -1,35 +0,0 @@
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+experimental-zbproposedc -show-encoding < %s \
-# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+experimental-zbproposedc -show-encoding \
-# RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+experimental-zbproposedc -filetype=obj < %s \
-# RUN: | llvm-objdump --triple=riscv32 --mattr=+c,+experimental-zbproposedc -d - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv32 -mattr=+c,+experimental-zbproposedc -filetype=obj < %s \
-# RUN: | llvm-objdump --triple=riscv32 --mattr=+c,+experimental-zbproposedc -d -M no-aliases - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc -show-encoding < %s \
-# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc -show-encoding \
-# RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc -filetype=obj < %s \
-# RUN: | llvm-objdump --triple=riscv64 --mattr=+c,+experimental-zbproposedc -d - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc -filetype=obj < %s \
-# RUN: | llvm-objdump --triple=riscv64 --mattr=+c,+experimental-zbproposedc -d -M no-aliases - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-
-# Tests bit manipulation instructions available in rv32 and in rv64.
-
-# CHECK-BYTES: 01 60
-# CHECK-ALIAS: not s0, s0
-# CHECK-INST: c.not s0
-# CHECK: # encoding: [0x01,0x60]
-not s0, s0
-
-# CHECK-BYTES: 01 64
-# CHECK-ALIAS: neg s0, s0
-# CHECK-INST: c.neg s0
-# CHECK: # encoding: [0x01,0x64]
-neg s0, s0
diff --git a/llvm/test/MC/RISCV/compress-rv64b.s b/llvm/test/MC/RISCV/compress-rv64b.s
deleted file mode 100644
index 43900d404e04f..0000000000000
--- a/llvm/test/MC/RISCV/compress-rv64b.s
+++ /dev/null
@@ -1,18 +0,0 @@
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b -show-encoding < %s \
-# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b -show-encoding \
-# RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b -filetype=obj < %s \
-# RUN: | llvm-objdump --triple=riscv64 --mattr=+c,+experimental-zbproposedc,+experimental-b -d - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b -filetype=obj < %s \
-# RUN: | llvm-objdump --triple=riscv64 --mattr=+c,+experimental-zbproposedc,+experimental-b -d -M no-aliases - \
-# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s
-
-# Tests compressed instructions available in rv64 and not in rv32.
-
-# CHECK-BYTES: 01 68
-# CHECK-ALIAS: zext.w s0, s0
-# CHECK-INST: c.zext.w s0
-# CHECK: # encoding: [0x01,0x68]
-zext.w s0, s0
diff --git a/llvm/test/MC/RISCV/rv32zbproposedc-invalid.s b/llvm/test/MC/RISCV/rv32zbproposedc-invalid.s
deleted file mode 100644
index 942852a34b1ec..0000000000000
--- a/llvm/test/MC/RISCV/rv32zbproposedc-invalid.s
+++ /dev/null
@@ -1,6 +0,0 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+c,+experimental-zbproposedc,+experimental-Zba < %s 2>&1 | FileCheck %s
-
-# Too many operands
-c.not s0, s1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
-c.neg s0, s1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
-c.zext.w s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
diff --git a/llvm/test/MC/RISCV/rv32zbproposedc-valid.s b/llvm/test/MC/RISCV/rv32zbproposedc-valid.s
deleted file mode 100644
index dd911d261390a..0000000000000
--- a/llvm/test/MC/RISCV/rv32zbproposedc-valid.s
+++ /dev/null
@@ -1,17 +0,0 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+experimental-zbproposedc -riscv-no-aliases -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b -riscv-no-aliases -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c,+experimental-zbproposedc < %s \
-# RUN: | llvm-objdump --mattr=+c,+experimental-zbproposedc -M no-aliases -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+c,+experimental-zbproposedc,+experimental-b -M no-aliases -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
-# CHECK-ASM-AND-OBJ: c.not s0
-# CHECK-ASM: encoding: [0x01,0x60]
-c.not s0
-# CHECK-ASM-AND-OBJ: c.neg s0
-# CHECK-ASM: encoding: [0x01,0x64]
-c.neg s0
diff --git a/llvm/test/MC/RISCV/rv64zbproposedc-invalid.s b/llvm/test/MC/RISCV/rv64zbproposedc-invalid.s
deleted file mode 100644
index 98accef76204b..0000000000000
--- a/llvm/test/MC/RISCV/rv64zbproposedc-invalid.s
+++ /dev/null
@@ -1,4 +0,0 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b < %s 2>&1 | FileCheck %s
-
-# Too many operands
-c.zext.w s0, s1 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64zbproposedc-valid.s b/llvm/test/MC/RISCV/rv64zbproposedc-valid.s
deleted file mode 100644
index a30f3bb85479b..0000000000000
--- a/llvm/test/MC/RISCV/rv64zbproposedc-valid.s
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b -riscv-no-aliases -show-encoding \
-# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+experimental-zbproposedc,+experimental-b < %s \
-# RUN: | llvm-objdump --mattr=+c,+experimental-zbproposedc,+experimental-b -M no-aliases -d -r - \
-# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
-
-# CHECK-ASM-AND-OBJ: c.zext.w s0
-# CHECK-ASM: encoding: [0x01,0x68]
-c.zext.w s0
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