[PATCH] D110231: [AMDGPU] Add constrained shift pattern matches.

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:2516
+multiclass ConstrainedShiftPat<int width> {
+  defvar mask = !sub(width, 1);
+  defvar ty = !cast<ValueType>("i" # width);
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abinavpp wrote:
> foad wrote:
> > `!sub(!shl(1, width), 1)`, surely?
> This mask is used to perform modulo width using `and`, i.e. 'RHS % width'. See clang's ScalarExprEmitter::ConstrainShiftValue() which is invoked by shift codegen `if (CGF.getLangOpts().OpenCL)`.
You are right of course, sorry for the noise.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110231/new/

https://reviews.llvm.org/D110231