[PATCH] D106449: [amdgpu] Handle the case where there is no scavenged register.

[Michael Liao via Phabricator via llvm-commits]

hliao marked 2 inline comments as done.
hliao added inline comments.


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Comment at: llvm/lib/CodeGen/BranchRelaxation.cpp:484-485
+    // restore blocks are just duplicated for each far branch.
+    if (DestBB->isEntryBlock()) {
+      // If DestBB is the entry block, create a new empty entry block falling
+      // through into DestBB.
----------------
arsenm wrote:
> I'm pretty sure this is illegal, you can't have a branch to the entry block
yeah, you are absolutely right!


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Comment at: llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll:331
+; CHECK-NEXT:    s_not_b64 exec, exec
+; CHECK-NEXT:    buffer_store_dword v0, off, s[96:99], 0
+; CHECK-NEXT:    v_writelane_b32 v0, s0, 0
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arsenm wrote:
> Where did this frame index come from?
That's the scavenge frame index previously added in https://reviews.llvm.org/D96336. Here, we need to spill an SGPR into a VGPR, which needs spilling into a frame slow when no VGPR could be scavenged.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106449/new/

https://reviews.llvm.org/D106449