[llvm] d3e2067 - [InstSimplify] add tests for (-1 << x) s>> x; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 29 08:45:26 PDT 2021
Author: Sanjay Patel
Date: 2021-09-29T11:43:18-04:00
New Revision: d3e2067c7c42200d487f7339e10b1e613576abef
URL: https://github.com/llvm/llvm-project/commit/d3e2067c7c42200d487f7339e10b1e613576abef
DIFF: https://github.com/llvm/llvm-project/commit/d3e2067c7c42200d487f7339e10b1e613576abef.diff
LOG: [InstSimplify] add tests for (-1 << x) s>> x; NFC
Added:
Modified:
llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll
llvm/test/Transforms/InstSimplify/shift.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll
index 3718ff47bf00b..c3039dc84fc52 100644
--- a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll
+++ b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-d.ll
@@ -252,9 +252,8 @@ define i32 @n6_extrause2(i64 %x, i32 %nbits) {
define i32 @PR51351(i64 %x, i32 %nbits) {
; CHECK-LABEL: @PR51351(
; CHECK-NEXT: [[T3:%.*]] = add i32 [[NBITS:%.*]], -33
-; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[X:%.*]] to i32
-; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[TMP1]], [[T3]]
-; CHECK-NEXT: [[T6:%.*]] = and i32 [[TMP2]], 2147483647
+; CHECK-NEXT: [[T5:%.*]] = trunc i64 [[X:%.*]] to i32
+; CHECK-NEXT: [[T6:%.*]] = shl i32 [[T5]], [[T3]]
; CHECK-NEXT: ret i32 [[T6]]
;
%t0 = zext i32 %nbits to i64
diff --git a/llvm/test/Transforms/InstSimplify/shift.ll b/llvm/test/Transforms/InstSimplify/shift.ll
index 725255b05c63f..fa144f6bddf87 100644
--- a/llvm/test/Transforms/InstSimplify/shift.ll
+++ b/llvm/test/Transforms/InstSimplify/shift.ll
@@ -177,65 +177,65 @@ define <2 x i8> @shl_by_sext_bool_vec(<2 x i1> %x, <2 x i8> %y) {
define i64 @shl_or_shr(i32 %a, i32 %b) {
; CHECK-LABEL: @shl_or_shr(
-; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
-; CHECK-NEXT: ret i64 [[TMP1]]
+; CHECK-NEXT: [[T1:%.*]] = zext i32 [[A:%.*]] to i64
+; CHECK-NEXT: ret i64 [[T1]]
;
- %tmp1 = zext i32 %a to i64
- %tmp2 = zext i32 %b to i64
- %tmp3 = shl nuw i64 %tmp1, 32
- %tmp4 = or i64 %tmp2, %tmp3
- %tmp5 = lshr i64 %tmp4, 32
- ret i64 %tmp5
+ %t1 = zext i32 %a to i64
+ %t2 = zext i32 %b to i64
+ %t3 = shl nuw i64 %t1, 32
+ %t4 = or i64 %t2, %t3
+ %t5 = lshr i64 %t4, 32
+ ret i64 %t5
}
; Since shift count of shl is smaller than the size of %b, OR cannot be eliminated.
define i64 @shl_or_shr2(i32 %a, i32 %b) {
; CHECK-LABEL: @shl_or_shr2(
-; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
-; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64
-; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 31
-; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 31
-; CHECK-NEXT: ret i64 [[TMP5]]
+; CHECK-NEXT: [[T1:%.*]] = zext i32 [[A:%.*]] to i64
+; CHECK-NEXT: [[T2:%.*]] = zext i32 [[B:%.*]] to i64
+; CHECK-NEXT: [[T3:%.*]] = shl nuw i64 [[T1]], 31
+; CHECK-NEXT: [[T4:%.*]] = or i64 [[T2]], [[T3]]
+; CHECK-NEXT: [[T5:%.*]] = lshr i64 [[T4]], 31
+; CHECK-NEXT: ret i64 [[T5]]
;
- %tmp1 = zext i32 %a to i64
- %tmp2 = zext i32 %b to i64
- %tmp3 = shl nuw i64 %tmp1, 31
- %tmp4 = or i64 %tmp2, %tmp3
- %tmp5 = lshr i64 %tmp4, 31
- ret i64 %tmp5
+ %t1 = zext i32 %a to i64
+ %t2 = zext i32 %b to i64
+ %t3 = shl nuw i64 %t1, 31
+ %t4 = or i64 %t2, %t3
+ %t5 = lshr i64 %t4, 31
+ ret i64 %t5
}
; Unit test for vector integer
define <2 x i64> @shl_or_shr1v(<2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: @shl_or_shr1v(
-; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
-; CHECK-NEXT: ret <2 x i64> [[TMP1]]
+; CHECK-NEXT: [[T1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
+; CHECK-NEXT: ret <2 x i64> [[T1]]
;
- %tmp1 = zext <2 x i32> %a to <2 x i64>
- %tmp2 = zext <2 x i32> %b to <2 x i64>
- %tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32>
- %tmp4 = or <2 x i64> %tmp3, %tmp2
- %tmp5 = lshr <2 x i64> %tmp4, <i64 32, i64 32>
- ret <2 x i64> %tmp5
+ %t1 = zext <2 x i32> %a to <2 x i64>
+ %t2 = zext <2 x i32> %b to <2 x i64>
+ %t3 = shl nuw <2 x i64> %t1, <i64 32, i64 32>
+ %t4 = or <2 x i64> %t3, %t2
+ %t5 = lshr <2 x i64> %t4, <i64 32, i64 32>
+ ret <2 x i64> %t5
}
; Negative unit test for vector integer
define <2 x i64> @shl_or_shr2v(<2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: @shl_or_shr2v(
-; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
-; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[B:%.*]] to <2 x i64>
-; CHECK-NEXT: [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], <i64 31, i64 31>
-; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i64> [[TMP2]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = lshr <2 x i64> [[TMP4]], <i64 31, i64 31>
-; CHECK-NEXT: ret <2 x i64> [[TMP5]]
+; CHECK-NEXT: [[T1:%.*]] = zext <2 x i32> [[A:%.*]] to <2 x i64>
+; CHECK-NEXT: [[T2:%.*]] = zext <2 x i32> [[B:%.*]] to <2 x i64>
+; CHECK-NEXT: [[T3:%.*]] = shl nuw <2 x i64> [[T1]], <i64 31, i64 31>
+; CHECK-NEXT: [[T4:%.*]] = or <2 x i64> [[T2]], [[T3]]
+; CHECK-NEXT: [[T5:%.*]] = lshr <2 x i64> [[T4]], <i64 31, i64 31>
+; CHECK-NEXT: ret <2 x i64> [[T5]]
;
- %tmp1 = zext <2 x i32> %a to <2 x i64>
- %tmp2 = zext <2 x i32> %b to <2 x i64>
- %tmp3 = shl nuw <2 x i64> %tmp1, <i64 31, i64 31>
- %tmp4 = or <2 x i64> %tmp2, %tmp3
- %tmp5 = lshr <2 x i64> %tmp4, <i64 31, i64 31>
- ret <2 x i64> %tmp5
+ %t1 = zext <2 x i32> %a to <2 x i64>
+ %t2 = zext <2 x i32> %b to <2 x i64>
+ %t3 = shl nuw <2 x i64> %t1, <i64 31, i64 31>
+ %t4 = or <2 x i64> %t2, %t3
+ %t5 = lshr <2 x i64> %t4, <i64 31, i64 31>
+ ret <2 x i64> %t5
}
define i32 @poison(i32 %x) {
@@ -285,3 +285,58 @@ define i32 @poison6(i32 %x) {
%v = shl i32 poison, %x
ret i32 %v
}
+
+define i32 @all_ones_left_right(i32 %x) {
+; CHECK-LABEL: @all_ones_left_right(
+; CHECK-NEXT: [[LEFT:%.*]] = shl i32 -1, [[X:%.*]]
+; CHECK-NEXT: [[RIGHT:%.*]] = ashr i32 [[LEFT]], [[X]]
+; CHECK-NEXT: ret i32 [[RIGHT]]
+;
+ %left = shl i32 -1, %x
+ %right = ashr i32 %left, %x
+ ret i32 %right
+}
+
+define <2 x i7> @all_ones_left_right_splat(<2 x i7> %x) {
+; CHECK-LABEL: @all_ones_left_right_splat(
+; CHECK-NEXT: [[LEFT:%.*]] = shl <2 x i7> <i7 -1, i7 -1>, [[X:%.*]]
+; CHECK-NEXT: [[RIGHT:%.*]] = ashr <2 x i7> [[LEFT]], [[X]]
+; CHECK-NEXT: ret <2 x i7> [[RIGHT]]
+;
+ %left = shl <2 x i7> <i7 -1, i7 -1>, %x
+ %right = ashr <2 x i7> %left, %x
+ ret <2 x i7> %right
+}
+
+define <3 x i7> @all_ones_left_right_splat_poison_undef_elt(<3 x i7> %x) {
+; CHECK-LABEL: @all_ones_left_right_splat_poison_undef_elt(
+; CHECK-NEXT: [[LEFT:%.*]] = shl <3 x i7> <i7 poison, i7 -1, i7 undef>, [[X:%.*]]
+; CHECK-NEXT: [[RIGHT:%.*]] = ashr <3 x i7> [[LEFT]], [[X]]
+; CHECK-NEXT: ret <3 x i7> [[RIGHT]]
+;
+ %left = shl <3 x i7> <i7 poison, i7 -1, i7 undef>, %x
+ %right = ashr <3 x i7> %left, %x
+ ret <3 x i7> %right
+}
+
+define i32 @almost_all_ones_left_right(i32 %x) {
+; CHECK-LABEL: @almost_all_ones_left_right(
+; CHECK-NEXT: [[LEFT:%.*]] = shl i32 -2, [[X:%.*]]
+; CHECK-NEXT: [[RIGHT:%.*]] = ashr i32 [[LEFT]], [[X]]
+; CHECK-NEXT: ret i32 [[RIGHT]]
+;
+ %left = shl i32 -2, %x
+ %right = ashr i32 %left, %x
+ ret i32 %right
+}
+
+define i32 @all_ones_left_right_not_same_shift(i32 %x, i32 %y) {
+; CHECK-LABEL: @all_ones_left_right_not_same_shift(
+; CHECK-NEXT: [[LEFT:%.*]] = shl i32 -1, [[X:%.*]]
+; CHECK-NEXT: [[RIGHT:%.*]] = ashr i32 [[LEFT]], [[Y:%.*]]
+; CHECK-NEXT: ret i32 [[RIGHT]]
+;
+ %left = shl i32 -1, %x
+ %right = ashr i32 %left, %y
+ ret i32 %right
+}
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