[PATCH] D110231: [AMDGPU] Add constrained shift pattern matches.
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 29 07:50:04 PDT 2021
foad added a comment.
> I think the PatFrags approach makes sense, but I'm a bit worried about the large
> scale substitution we have to do in all the generic shift opcode references in
> all the Target/AMDGPU .td files.
I was hoping we could define something like this (I'm not sure of the exact syntax):
def ShiftAmount32 : PatFrags<(ops node:$src), [(i32 $src), (and (i32 $src), 31)]>;
This would match either a raw shift amount or a shift amount ANDed with 31. Then we could change every pattern that currently contains `(shl $a, $b)` to `(shl $a, (ShiftAmount32 $b))` instead. Yes this will touch every pattern that mentions a generic shift opcode, but I think it's the right thing to do.
> As @foad mentioned, it will be neater if we do (<shift> a, (and b, <width> - 1))
> -> (<shift> a, b) in AMDGPU specific compilation where the target <shift> is
> generic so that the other generic shift based pattern match (like the v_lshl_add
> pattern match) will work. The problem here is that we'll be violating the
> generic shift's semantics and, as @arsenm mentioned, creating custom nodes will
> be painful.
I agree with Matt that this was not a good idea.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D110231/new/
https://reviews.llvm.org/D110231
More information about the llvm-commits
mailing list