[PATCH] D110390: [SCEV] Establish control over disposition caches

[Max Kazantsev via Phabricator via llvm-commits]

mkazantsev added a comment.

The only theory I have so far is that this hypothetical SCEV isn't bound to instruction, but still is available somewhere (like, it's some loop's backedge count). I'll check this. However, the situation is worrysome even if so. We don't control which SCEVs are hypothetical and which are not, and create tons of them.


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  https://reviews.llvm.org/D110390/new/

https://reviews.llvm.org/D110390