[llvm] 87bcbd6 - [AArch64][SVE] Fix extract_subvector patterns for unpacked fp types.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 29 03:15:28 PDT 2021
Author: Sander de Smalen
Date: 2021-09-29T11:14:49+01:00
New Revision: 87bcbd61b5e60ed1f465cc276029be9f667162ba
URL: https://github.com/llvm/llvm-project/commit/87bcbd61b5e60ed1f465cc276029be9f667162ba
DIFF: https://github.com/llvm/llvm-project/commit/87bcbd61b5e60ed1f465cc276029be9f667162ba.diff
LOG: [AArch64][SVE] Fix extract_subvector patterns for unpacked fp types.
The patterns added in D110163 were incorrect, since it used the wrong
element widths for its shuffles.
Example for nxv2f16 extract_subvector(nxv8f16 %in, 6):
<a|b|c|d|e|f|g|h>
^^^
extract g and h.
=> UUNPKHI .h -> .s results in:
<e |f |g |h >
=> UUNPKHI .s -> .d results in:
<g |h >
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D110523
Added:
Modified:
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 0911ecdeaea1..6199d4e33be1 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1333,22 +1333,22 @@ let Predicates = [HasSVEorStreamingSVE] in {
(UUNPKHI_ZZ_S ZPR:$Zs)>;
def : Pat<(nxv2f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 0))),
- (UUNPKLO_ZZ_S (UUNPKLO_ZZ_D ZPR:$Zs))>;
+ (UUNPKLO_ZZ_D (UUNPKLO_ZZ_S ZPR:$Zs))>;
def : Pat<(nxv2f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 2))),
- (UUNPKHI_ZZ_S (UUNPKLO_ZZ_D ZPR:$Zs))>;
+ (UUNPKHI_ZZ_D (UUNPKLO_ZZ_S ZPR:$Zs))>;
def : Pat<(nxv2f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 4))),
- (UUNPKLO_ZZ_S (UUNPKHI_ZZ_D ZPR:$Zs))>;
+ (UUNPKLO_ZZ_D (UUNPKHI_ZZ_S ZPR:$Zs))>;
def : Pat<(nxv2f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 6))),
- (UUNPKHI_ZZ_S (UUNPKHI_ZZ_D ZPR:$Zs))>;
+ (UUNPKHI_ZZ_D (UUNPKHI_ZZ_S ZPR:$Zs))>;
def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 0))),
- (UUNPKLO_ZZ_S (UUNPKLO_ZZ_D ZPR:$Zs))>;
+ (UUNPKLO_ZZ_D (UUNPKLO_ZZ_S ZPR:$Zs))>;
def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 2))),
- (UUNPKHI_ZZ_S (UUNPKLO_ZZ_D ZPR:$Zs))>;
+ (UUNPKHI_ZZ_D (UUNPKLO_ZZ_S ZPR:$Zs))>;
def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 4))),
- (UUNPKLO_ZZ_S (UUNPKHI_ZZ_D ZPR:$Zs))>;
+ (UUNPKLO_ZZ_D (UUNPKHI_ZZ_S ZPR:$Zs))>;
def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 6))),
- (UUNPKHI_ZZ_S (UUNPKHI_ZZ_D ZPR:$Zs))>;
+ (UUNPKHI_ZZ_D (UUNPKHI_ZZ_S ZPR:$Zs))>;
// Concatenate two predicates.
def : Pat<(nxv4i1 (concat_vectors nxv2i1:$p1, nxv2i1:$p2)),
diff --git a/llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll b/llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
index 5f5936438114..4367db6f53c6 100644
--- a/llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
+++ b/llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
@@ -502,8 +502,8 @@ declare <vscale x 4 x i8> @llvm.experimental.vector.extract.nxv4i8.nxv16i8(<vsca
define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_0(<vscale x 6 x half> %in) {
; CHECK-LABEL: extract_nxv2f16_nxv6f16_0:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half> %in, i64 0)
ret <vscale x 2 x half> %res
@@ -512,8 +512,8 @@ define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_0(<vscale x 6 x half> %in) {
define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_2(<vscale x 6 x half> %in) {
; CHECK-LABEL: extract_nxv2f16_nxv6f16_2:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpklo z0.d, z0.s
-; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half> %in, i64 2)
ret <vscale x 2 x half> %res
@@ -522,8 +522,8 @@ define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_2(<vscale x 6 x half> %in) {
define <vscale x 2 x half> @extract_nxv2f16_nxv6f16_4(<vscale x 6 x half> %in) {
; CHECK-LABEL: extract_nxv2f16_nxv6f16_4:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv6f16(<vscale x 6 x half> %in, i64 4)
ret <vscale x 2 x half> %res
@@ -601,8 +601,8 @@ declare <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv16f16(<
define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_0(<vscale x 8 x half> %in) {
; CHECK-LABEL: extract_nxv2f16_nxv8f16_0:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 0)
ret <vscale x 2 x half> %res
@@ -611,8 +611,8 @@ define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_0(<vscale x 8 x half> %in) {
define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_2(<vscale x 8 x half> %in) {
; CHECK-LABEL: extract_nxv2f16_nxv8f16_2:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpklo z0.d, z0.s
-; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 2)
ret <vscale x 2 x half> %res
@@ -621,8 +621,8 @@ define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_2(<vscale x 8 x half> %in) {
define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_4(<vscale x 8 x half> %in) {
; CHECK-LABEL: extract_nxv2f16_nxv8f16_4:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 4)
ret <vscale x 2 x half> %res
@@ -631,8 +631,8 @@ define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_4(<vscale x 8 x half> %in) {
define <vscale x 2 x half> @extract_nxv2f16_nxv8f16_6(<vscale x 8 x half> %in) {
; CHECK-LABEL: extract_nxv2f16_nxv8f16_6:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.extract.nxv2f16.nxv8f16(<vscale x 8 x half> %in, i64 6)
ret <vscale x 2 x half> %res
@@ -669,8 +669,8 @@ declare <vscale x 4 x bfloat> @llvm.experimental.vector.extract.nxv4bf16.nxv8bf1
define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_0(<vscale x 6 x bfloat> %in) {
; CHECK-LABEL: extract_nxv2bf16_nxv6bf16_0:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret
%res = call <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat> %in, i64 0)
ret <vscale x 2 x bfloat> %res
@@ -679,8 +679,8 @@ define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_0(<vscale x 6 x bfloat>
define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_2(<vscale x 6 x bfloat> %in) {
; CHECK-LABEL: extract_nxv2bf16_nxv6bf16_2:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpklo z0.d, z0.s
-; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret
%res = call <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat> %in, i64 2)
ret <vscale x 2 x bfloat> %res
@@ -689,8 +689,8 @@ define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_2(<vscale x 6 x bfloat>
define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv6bf16_4(<vscale x 6 x bfloat> %in) {
; CHECK-LABEL: extract_nxv2bf16_nxv6bf16_4:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret
%res = call <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv6bf16(<vscale x 6 x bfloat> %in, i64 4)
ret <vscale x 2 x bfloat> %res
@@ -704,8 +704,8 @@ declare <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv6bf1
define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_0(<vscale x 8 x bfloat> %in) {
; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_0:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret
%res = call <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 0)
ret <vscale x 2 x bfloat> %res
@@ -714,8 +714,8 @@ define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_0(<vscale x 8 x bfloat>
define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_2(<vscale x 8 x bfloat> %in) {
; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_2:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpklo z0.d, z0.s
-; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret
%res = call <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 2)
ret <vscale x 2 x bfloat> %res
@@ -724,8 +724,8 @@ define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_2(<vscale x 8 x bfloat>
define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_4(<vscale x 8 x bfloat> %in) {
; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_4:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpkhi z0.d, z0.s
-; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ret
%res = call <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 4)
ret <vscale x 2 x bfloat> %res
@@ -734,8 +734,8 @@ define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_4(<vscale x 8 x bfloat>
define <vscale x 2 x bfloat> @extract_nxv2bf16_nxv8bf16_6(<vscale x 8 x bfloat> %in) {
; CHECK-LABEL: extract_nxv2bf16_nxv8bf16_6:
; CHECK: // %bb.0:
-; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: uunpkhi z0.s, z0.h
+; CHECK-NEXT: uunpkhi z0.d, z0.s
; CHECK-NEXT: ret
%res = call <vscale x 2 x bfloat> @llvm.experimental.vector.extract.nxv2bf16.nxv8bf16(<vscale x 8 x bfloat> %in, i64 6)
ret <vscale x 2 x bfloat> %res
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