[PATCH] D109963: [AArch64] Split bitmask immediate of bitwise AND operation

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 added a comment.

In D109963#3029409 <https://reviews.llvm.org/D109963#3029409>, @dmgreen wrote:

> I don't think this needs to create all the COPY's, if it calls constrainRegClass on the registers to ensure they do not contain the wrong set of registers.

You are right! We can constrain the register class to `GPR[32|64]common`. Thanks @dmgreen. Let me update it.


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