[PATCH] D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled

[David Sherwood via Phabricator via llvm-commits]

david-arm accepted this revision.
david-arm added a comment.
This revision is now accepted and ready to land.

LGTM! Thanks for making the changes.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:9471
+    if (ExtractedValType.isFixedLengthVector() &&
+        ExtractedValType.getSizeInBits().getValue() <= 128) {
+      Lane += V.getConstantOperandVal(1);
----------------
nit: Before committing could you change this to:

  ExtractedValType.getFixedSizeInBits()

It's a bit shorter and it also asserts that the TypeSize is fixed.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110524/new/

https://reviews.llvm.org/D110524