[PATCH] D108129: [DAGCombiner] Teach combineShiftToMULH to handle constant and const splat vector.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added a comment.

In D108129#3025471 <https://reviews.llvm.org/D108129#3025471>, @RKSimon wrote:

> Can the tests be pre-commited to trunk so we can see the effect of the patch on codegen?

Done, I pre-commited these tests in D110675 <https://reviews.llvm.org/D110675>.



================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:8528
+
+  ConstantSDNode *Constant = isConstOrConstSplat(RightOp);
+  SDValue MulhRightOp;
----------------
craig.topper wrote:
> Fold this into the if on line 8530 to limit the scope of Constant
Done, thanks a lot.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:8533
+    if (IsSignExt) {
+      // If is negative constant, should cout with the signed bit.
+      bool IsSignedConstant = Constant->getAPIntValue().isNegative();
----------------
craig.topper wrote:
> Why can't we use getMinSignedBits() for signed and getActiveBits() for unsigned.
Done, thanks a lot.


Repository:
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  https://reviews.llvm.org/D108129/new/

https://reviews.llvm.org/D108129