[PATCH] D107160: [AArch64] Do not emit an extra zero-extend for i1 argument

[Amara Emerson via Phabricator via llvm-commits]

aemerson added inline comments.


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp:553
+        Register OrigReg = OrigArg.Regs[0];
+        Register WideReg = MRI.createGenericVirtualRegister(LLT(MVT::i8));
+        OrigArg.Regs[0] = WideReg;
----------------
This can be `LLT::scalar(8)`


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp:587
+          MIRBuilder
+              .buildAssertZExt(WideTy, WideReg, OrigTy.getScalarSizeInBits())
+              .getReg(0);
----------------
If these are bool args then we can assume OrigTy.getScalarSizeInBits() == 1 right?


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp:588-589
+              .buildAssertZExt(WideTy, WideReg, OrigTy.getScalarSizeInBits())
+              .getReg(0);
+      MIRBuilder.buildTrunc(OrigReg, WideReg);
+    }
----------------
MIRBuilder's builder methods return a MachineInstrBuilder that can be directly passed into most source operands of other builder methods. You can simplify these lines into something like:
```
MIRBuilder.buildTrunc(OrigReg, MIRBuilder.buildAssertZExt(WideTy, WideReg, 1));
```



Repository:
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  https://reviews.llvm.org/D107160/new/

https://reviews.llvm.org/D107160