[llvm] 2c53215 - [ARM] Skip debug info in recomputeVPTBlockMask
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 28 06:58:19 PDT 2021
Author: David Green
Date: 2021-09-28T14:58:13+01:00
New Revision: 2c53215e99cbd7b24768d9f0915aff9fedfcaa4a
URL: https://github.com/llvm/llvm-project/commit/2c53215e99cbd7b24768d9f0915aff9fedfcaa4a
DIFF: https://github.com/llvm/llvm-project/commit/2c53215e99cbd7b24768d9f0915aff9fedfcaa4a.diff
LOG: [ARM] Skip debug info in recomputeVPTBlockMask
The ARMLowOverheadLoops pass recalculates VPT block masks when it
converts VCMP's inside VPT blocks into VPT's. The function to do so
doesn't seem to handle debug info though, leading to invalid block
creation or asserts at compile time. Make sure the function skips any
debug info between the MVE instructions it inspects.
Differential Revision: https://reviews.llvm.org/D110564
Added:
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-block-debug.mir
Modified:
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
index 5204e3b03e9e3..4898a4b77761f 100644
--- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -792,8 +792,12 @@ void llvm::recomputeVPTBlockMask(MachineInstr &Instr) {
MachineBasicBlock::iterator Iter = ++Instr.getIterator(),
End = Instr.getParent()->end();
+ while (Iter != End && Iter->isDebugInstr())
+ ++Iter;
+
// Verify that the instruction after the VPT/VPST is predicated (it should
// be), and skip it.
+ assert(Iter != End && "Expected some instructions in any VPT block");
assert(
getVPTInstrPredicate(*Iter) == ARMVCC::Then &&
"VPT/VPST should be followed by an instruction with a 'then' predicate!");
@@ -802,6 +806,10 @@ void llvm::recomputeVPTBlockMask(MachineInstr &Instr) {
// Iterate over the predicated instructions, updating the BlockMask as we go.
ARM::PredBlockMask BlockMask = ARM::PredBlockMask::T;
while (Iter != End) {
+ if (Iter->isDebugInstr()) {
+ ++Iter;
+ continue;
+ }
ARMVCC::VPTCodes Pred = getVPTInstrPredicate(*Iter);
if (Pred == ARMVCC::None)
break;
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-block-debug.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-block-debug.mir
new file mode 100644
index 0000000000000..9f2a7d9fb510b
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-block-debug.mir
@@ -0,0 +1,452 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+ target triple = "thumbv8.1m.main-arm-none-eabi"
+
+ %struct.arm_2d_size_t = type { i16, i16 }
+
+ define void @__arm_2d_impl_rgb16_cl_key_1x1_paving_x_mirror_xx(i16* noalias %pSource, i16 signext %iSourceStride, i16* noalias %pTarget, i16 signext %iTargetStride, %struct.arm_2d_size_t* noalias nocapture readonly %ptSrcCopySize, %struct.arm_2d_size_t* noalias nocapture readonly %ptDstCopySize, i16 zeroext %Colour) local_unnamed_addr #0 !dbg !12 {
+ entry:
+ call void @llvm.dbg.value(metadata i16* %pSource, metadata !33, metadata !DIExpression()), !dbg !62
+ call void @llvm.dbg.value(metadata i16 %iSourceStride, metadata !34, metadata !DIExpression()), !dbg !62
+ call void @llvm.dbg.value(metadata i16* %pTarget, metadata !35, metadata !DIExpression()), !dbg !62
+ call void @llvm.dbg.value(metadata i16 %iTargetStride, metadata !36, metadata !DIExpression()), !dbg !62
+ call void @llvm.dbg.value(metadata %struct.arm_2d_size_t* %ptSrcCopySize, metadata !37, metadata !DIExpression()), !dbg !62
+ call void @llvm.dbg.value(metadata %struct.arm_2d_size_t* %ptDstCopySize, metadata !38, metadata !DIExpression()), !dbg !62
+ call void @llvm.dbg.value(metadata i16 %Colour, metadata !39, metadata !DIExpression()), !dbg !62
+ call void @llvm.dbg.value(metadata i16 undef, metadata !40, metadata !DIExpression(DW_OP_LLVM_convert, 16, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value)), !dbg !62
+ call void @llvm.dbg.value(metadata i32 0, metadata !43, metadata !DIExpression()), !dbg !63
+ %iHeight = getelementptr inbounds %struct.arm_2d_size_t, %struct.arm_2d_size_t* %ptDstCopySize, i32 0, i32 1
+ %0 = load i16, i16* %iHeight, align 2, !tbaa !64
+ %conv1 = sext i16 %0 to i32
+ %conv8 = sext i16 %iSourceStride to i32
+ %conv10 = sext i16 %iTargetStride to i32
+ call void @llvm.dbg.value(metadata i16* %pSource, metadata !33, metadata !DIExpression()), !dbg !62
+ call void @llvm.dbg.value(metadata i16* %pTarget, metadata !35, metadata !DIExpression()), !dbg !62
+ call void @llvm.dbg.value(metadata i32 0, metadata !43, metadata !DIExpression()), !dbg !63
+ %cmp34 = icmp sgt i16 %0, 0, !dbg !69
+ br i1 %cmp34, label %for.body.lr.ph, label %for.cond.cleanup, !dbg !70
+
+ for.body.lr.ph: ; preds = %entry
+ %iWidth2 = bitcast %struct.arm_2d_size_t* %ptSrcCopySize to i16*, !dbg !71
+ %1 = load i16, i16* %iWidth2, align 2, !dbg !71, !tbaa !72
+ call void @llvm.dbg.value(metadata i16 %1, metadata !40, metadata !DIExpression(DW_OP_LLVM_convert, 16, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value)), !dbg !62
+ %conv = sext i16 %1 to i32, !dbg !73
+ call void @llvm.dbg.value(metadata i32 %conv, metadata !40, metadata !DIExpression()), !dbg !62
+ %sub = add nsw i32 %conv, -1
+ %iWidth33 = bitcast %struct.arm_2d_size_t* %ptDstCopySize to i16*
+ %2 = load i16, i16* %iWidth33, align 2, !tbaa !72
+ %conv4 = sext i16 %2 to i32
+ %3 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32 %sub, i32 1), !dbg !62
+ %4 = add i32 %conv4, 7, !dbg !70
+ %smin = call i32 @llvm.smin.i32(i32 %conv4, i32 8), !dbg !70
+ %5 = sub i32 %4, %smin, !dbg !70
+ %6 = lshr i32 %5, 3, !dbg !70
+ %7 = add nuw nsw i32 %6, 1, !dbg !70
+ br label %for.body, !dbg !70
+
+ for.cond.cleanup: ; preds = %do.end, %entry
+ ret void, !dbg !74
+
+ for.body: ; preds = %do.end, %for.body.lr.ph
+ %pSource.addr.037 = phi i16* [ %pSource, %for.body.lr.ph ], [ %add.ptr9, %do.end ]
+ %pTarget.addr.036 = phi i16* [ %pTarget, %for.body.lr.ph ], [ %add.ptr11, %do.end ]
+ %y.035 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %do.end ]
+ call void @llvm.dbg.value(metadata i16* %pSource.addr.037, metadata !33, metadata !DIExpression()), !dbg !62
+ call void @llvm.dbg.value(metadata i16* %pTarget.addr.036, metadata !35, metadata !DIExpression()), !dbg !62
+ call void @llvm.dbg.value(metadata i32 %y.035, metadata !43, metadata !DIExpression()), !dbg !63
+ call void @llvm.dbg.value(metadata i16* %pTarget.addr.036, metadata !46, metadata !DIExpression()), !dbg !75
+ call void @llvm.dbg.value(metadata i16* %pSource.addr.037, metadata !49, metadata !DIExpression()), !dbg !75
+ call void @llvm.dbg.value(metadata i32 %conv4, metadata !50, metadata !DIExpression()), !dbg !75
+ call void @llvm.dbg.value(metadata i32 undef, metadata !51, metadata !DIExpression()), !dbg !75
+ call void @llvm.dbg.value(metadata <8 x i16> undef, metadata !52, metadata !DIExpression()), !dbg !75
+ %8 = call i32 @llvm.start.loop.iterations.i32(i32 %7), !dbg !76
+ br label %do.body, !dbg !76
+
+ do.body: ; preds = %do.body, %for.body
+ %pDst.0 = phi i16* [ %pTarget.addr.036, %for.body ], [ %add.ptr, %do.body ], !dbg !75
+ %dstWidth.0 = phi i32 [ %conv4, %for.body ], [ %sub5, %do.body ], !dbg !75
+ %.pn = phi { <8 x i16>, i32 } [ %3, %for.body ], [ %12, %do.body ]
+ %9 = phi i32 [ %8, %for.body ], [ %17, %do.body ], !dbg !75
+ %pDst.01 = bitcast i16* %pDst.0 to <8 x i16>*, !dbg !75
+ %offset.0 = extractvalue { <8 x i16>, i32 } %.pn, 0, !dbg !75
+ %curOffsetIdx.0 = extractvalue { <8 x i16>, i32 } %.pn, 1, !dbg !75
+ call void @llvm.dbg.value(metadata <8 x i16> %offset.0, metadata !52, metadata !DIExpression()), !dbg !75
+ call void @llvm.dbg.value(metadata i32 %curOffsetIdx.0, metadata !51, metadata !DIExpression()), !dbg !75
+ call void @llvm.dbg.value(metadata i32 %dstWidth.0, metadata !50, metadata !DIExpression()), !dbg !75
+ call void @llvm.dbg.value(metadata i16* %pDst.0, metadata !46, metadata !DIExpression()), !dbg !75
+ %10 = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %dstWidth.0), !dbg !77
+ call void @llvm.dbg.value(metadata i32 undef, metadata !58, metadata !DIExpression()), !dbg !78
+ %11 = tail call <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0i16.v8i16.v8i1(i16* %pSource.addr.037, <8 x i16> %offset.0, i32 16, i32 1, i32 1, <8 x i1> %10), !dbg !79
+ call void @llvm.dbg.value(metadata <8 x i16> %11, metadata !61, metadata !DIExpression()), !dbg !78
+ %12 = tail call { <8 x i16>, i32 } @llvm.arm.mve.vddup.predicated.v8i16.v8i1(<8 x i16> undef, i32 %curOffsetIdx.0, i32 1, <8 x i1> %10), !dbg !80
+ call void @llvm.dbg.value(metadata i32 undef, metadata !51, metadata !DIExpression()), !dbg !75
+ call void @llvm.dbg.value(metadata <8 x i16> undef, metadata !52, metadata !DIExpression()), !dbg !75
+ %13 = insertelement <8 x i16> poison, i16 %Colour, i32 0
+ %14 = shufflevector <8 x i16> %13, <8 x i16> poison, <8 x i32> zeroinitializer
+ %15 = icmp ne <8 x i16> %11, %14, !dbg !81
+ %16 = and <8 x i1> %15, %10, !dbg !81
+ call void @llvm.dbg.value(metadata i32 undef, metadata !58, metadata !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 16, DW_ATE_unsigned, DW_OP_stack_value)), !dbg !78
+ tail call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %11, <8 x i16>* %pDst.01, i32 2, <8 x i1> %16), !dbg !82
+ %add.ptr = getelementptr inbounds i16, i16* %pDst.0, i32 8, !dbg !83
+ call void @llvm.dbg.value(metadata i16* %add.ptr, metadata !46, metadata !DIExpression()), !dbg !75
+ %sub5 = add nsw i32 %dstWidth.0, -8, !dbg !84
+ call void @llvm.dbg.value(metadata i32 %sub5, metadata !50, metadata !DIExpression()), !dbg !75
+ %17 = call i32 @llvm.loop.decrement.reg.i32(i32 %9, i32 1), !dbg !85
+ %18 = icmp ne i32 %17, 0, !dbg !85
+ br i1 %18, label %do.body, label %do.end, !dbg !85, !llvm.loop !86
+
+ do.end: ; preds = %do.body
+ %add.ptr9 = getelementptr inbounds i16, i16* %pSource.addr.037, i32 %conv8, !dbg !89
+ call void @llvm.dbg.value(metadata i16* %add.ptr9, metadata !33, metadata !DIExpression()), !dbg !62
+ %add.ptr11 = getelementptr inbounds i16, i16* %pTarget.addr.036, i32 %conv10, !dbg !90
+ call void @llvm.dbg.value(metadata i16* %add.ptr11, metadata !35, metadata !DIExpression()), !dbg !62
+ %inc = add nuw nsw i32 %y.035, 1, !dbg !91
+ call void @llvm.dbg.value(metadata i32 %inc, metadata !43, metadata !DIExpression()), !dbg !63
+ %exitcond.not = icmp eq i32 %inc, %conv1, !dbg !69
+ br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !dbg !70, !llvm.loop !92
+ }
+
+ declare { <8 x i16>, i32 } @llvm.arm.mve.vddup.v8i16(i32, i32)
+ declare <8 x i1> @llvm.arm.mve.vctp16(i32)
+ declare <8 x i16> @llvm.arm.mve.vldr.gather.offset.predicated.v8i16.p0i16.v8i16.v8i1(i16*, <8 x i16>, i32, i32, i32, <8 x i1>)
+ declare { <8 x i16>, i32 } @llvm.arm.mve.vddup.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>)
+ declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>)
+ declare void @llvm.dbg.value(metadata, metadata, metadata)
+ declare i32 @llvm.smin.i32(i32, i32)
+ declare i32 @llvm.start.loop.iterations.i32(i32)
+ declare i32 @llvm.loop.decrement.reg.i32(i32, i32)
+
+ attributes #0 = { nofree nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+cdecp0,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8sp,-fp16fml,-hwdiv-arm,-i8mm,-neon,-sb,-sha2,-vfp3,-vfp3sp,-vfp4,-vfp4sp" "unsafe-fp-math"="true" }
+
+ !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, retainedTypes: !2, splitDebugInlining: false, nameTableKind: None)
+ !1 = !DIFile(filename: "tmp.c", directory: "")
+ !2 = !{!3}
+ !3 = !DIDerivedType(tag: DW_TAG_typedef, name: "int32_t", file: !4, line: 58, baseType: !5)
+ !4 = !DIFile(filename: "stdint.h", directory: "")
+ !5 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+ !6 = !{i32 7, !"Dwarf Version", i32 4}
+ !7 = !{i32 2, !"Debug Info Version", i32 3}
+ !8 = !{i32 1, !"wchar_size", i32 4}
+ !9 = !{i32 1, !"min_enum_size", i32 4}
+ !10 = !{i32 7, !"frame-pointer", i32 2}
+ !11 = !{!"clang"}
+ !12 = distinct !DISubprogram(name: "__arm_2d_impl_rgb16_cl_key_1x1_paving_x_mirror_xx", scope: !1, file: !1, line: 61, type: !13, scopeLine: 71, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !32)
+ !13 = !DISubroutineType(types: !14)
+ !14 = !{null, !15, !20, !22, !20, !24, !24, !18}
+ !15 = !DIDerivedType(tag: DW_TAG_restrict_type, baseType: !16)
+ !16 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !17, size: 32)
+ !17 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !18)
+ !18 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint16_t", file: !4, line: 63, baseType: !19)
+ !19 = !DIBasicType(name: "unsigned short", size: 16, encoding: DW_ATE_unsigned)
+ !20 = !DIDerivedType(tag: DW_TAG_typedef, name: "int16_t", file: !4, line: 57, baseType: !21)
+ !21 = !DIBasicType(name: "short", size: 16, encoding: DW_ATE_signed)
+ !22 = !DIDerivedType(tag: DW_TAG_restrict_type, baseType: !23)
+ !23 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !18, size: 32)
+ !24 = !DIDerivedType(tag: DW_TAG_restrict_type, baseType: !25)
+ !25 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !26, size: 32)
+ !26 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !27)
+ !27 = !DIDerivedType(tag: DW_TAG_typedef, name: "arm_2d_size_t", file: !1, line: 8, baseType: !28)
+ !28 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "arm_2d_size_t", file: !1, line: 5, size: 32, elements: !29)
+ !29 = !{!30, !31}
+ !30 = !DIDerivedType(tag: DW_TAG_member, name: "iWidth", scope: !28, file: !1, line: 6, baseType: !20, size: 16)
+ !31 = !DIDerivedType(tag: DW_TAG_member, name: "iHeight", scope: !28, file: !1, line: 7, baseType: !20, size: 16, offset: 16)
+ !32 = !{!33, !34, !35, !36, !37, !38, !39, !40, !43, !46, !49, !50, !51, !52, !58, !61}
+ !33 = !DILocalVariable(name: "pSource", arg: 1, scope: !12, file: !1, line: 62, type: !15)
+ !34 = !DILocalVariable(name: "iSourceStride", arg: 2, scope: !12, file: !1, line: 63, type: !20)
+ !35 = !DILocalVariable(name: "pTarget", arg: 3, scope: !12, file: !1, line: 64, type: !22)
+ !36 = !DILocalVariable(name: "iTargetStride", arg: 4, scope: !12, file: !1, line: 65, type: !20)
+ !37 = !DILocalVariable(name: "ptSrcCopySize", arg: 5, scope: !12, file: !1, line: 67, type: !24)
+ !38 = !DILocalVariable(name: "ptDstCopySize", arg: 6, scope: !12, file: !1, line: 69, type: !24)
+ !39 = !DILocalVariable(name: "Colour", arg: 7, scope: !12, file: !1, line: 70, type: !18)
+ !40 = !DILocalVariable(name: "srcWidth", scope: !12, file: !1, line: 72, type: !41)
+ !41 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint32_t", file: !4, line: 64, baseType: !42)
+ !42 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned)
+ !43 = !DILocalVariable(name: "y", scope: !44, file: !1, line: 74, type: !45)
+ !44 = distinct !DILexicalBlock(scope: !12, file: !1, line: 74, column: 5)
+ !45 = !DIDerivedType(tag: DW_TAG_typedef, name: "int_fast16_t", file: !4, line: 86, baseType: !5)
+ !46 = !DILocalVariable(name: "pDst", scope: !47, file: !1, line: 75, type: !23)
+ !47 = distinct !DILexicalBlock(scope: !48, file: !1, line: 74, column: 63)
+ !48 = distinct !DILexicalBlock(scope: !44, file: !1, line: 74, column: 5)
+ !49 = !DILocalVariable(name: "pSrc", scope: !47, file: !1, line: 76, type: !15)
+ !50 = !DILocalVariable(name: "dstWidth", scope: !47, file: !1, line: 77, type: !41)
+ !51 = !DILocalVariable(name: "curOffsetIdx", scope: !47, file: !1, line: 78, type: !41)
+ !52 = !DILocalVariable(name: "offset", scope: !47, file: !1, line: 79, type: !53)
+ !53 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint16x8_t", file: !54, line: 37, baseType: !55)
+ !54 = !DIFile(filename: "lib/clang/14.0.0/include/arm_mve.h", directory: "")
+ !55 = !DICompositeType(tag: DW_TAG_array_type, baseType: !18, size: 128, flags: DIFlagVector, elements: !56)
+ !56 = !{!57}
+ !57 = !DISubrange(count: 8)
+ !58 = !DILocalVariable(name: "p", scope: !59, file: !1, line: 81, type: !60)
+ !59 = distinct !DILexicalBlock(scope: !47, file: !1, line: 80, column: 12)
+ !60 = !DIDerivedType(tag: DW_TAG_typedef, name: "mve_pred16_t", file: !54, line: 24, baseType: !18)
+ !61 = !DILocalVariable(name: "in", scope: !59, file: !1, line: 82, type: !53)
+ !62 = !DILocation(line: 0, scope: !12)
+ !63 = !DILocation(line: 0, scope: !44)
+ !64 = !{!65, !66, i64 2}
+ !65 = !{!"arm_2d_size_t", !66, i64 0, !66, i64 2}
+ !66 = !{!"short", !67, i64 0}
+ !67 = !{!"omnipotent char", !68, i64 0}
+ !68 = !{!"Simple C/C++ TBAA"}
+ !69 = !DILocation(line: 74, column: 32, scope: !48)
+ !70 = !DILocation(line: 74, column: 5, scope: !44)
+ !71 = !DILocation(line: 72, column: 47, scope: !12)
+ !72 = !{!65, !66, i64 0}
+ !73 = !DILocation(line: 72, column: 32, scope: !12)
+ !74 = !DILocation(line: 93, column: 1, scope: !12)
+ !75 = !DILocation(line: 0, scope: !47)
+ !76 = !DILocation(line: 80, column: 9, scope: !47)
+ !77 = !DILocation(line: 81, column: 33, scope: !59)
+ !78 = !DILocation(line: 0, scope: !59)
+ !79 = !DILocation(line: 83, column: 18, scope: !59)
+ !80 = !DILocation(line: 84, column: 22, scope: !59)
+ !81 = !DILocation(line: 85, column: 17, scope: !59)
+ !82 = !DILocation(line: 86, column: 13, scope: !59)
+ !83 = !DILocation(line: 87, column: 18, scope: !59)
+ !84 = !DILocation(line: 88, column: 22, scope: !59)
+ !85 = !DILocation(line: 89, column: 9, scope: !59)
+ !86 = distinct !{!86, !76, !87, !88}
+ !87 = !DILocation(line: 89, column: 40, scope: !47)
+ !88 = !{!"llvm.loop.mustprogress"}
+ !89 = !DILocation(line: 90, column: 17, scope: !47)
+ !90 = !DILocation(line: 91, column: 17, scope: !47)
+ !91 = !DILocation(line: 74, column: 59, scope: !48)
+ !92 = distinct !{!92, !70, !93, !88}
+ !93 = !DILocation(line: 92, column: 5, scope: !44)
+
+...
+---
+name: __arm_2d_impl_rgb16_cl_key_1x1_paving_x_mirror_xx
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+ - { reg: '$r3', virtual-reg: '' }
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 40
+ offsetAdjustment: -32
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 0
+ cvBytesOfCalleeSavedRegisters: 0
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ hasTailCall: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 2, type: default, offset: 0, size: 4, alignment: 8, stack-id: default,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 3, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 4, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 5, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 6, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r11', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 7, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 8, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 9, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body: |
+ ; CHECK-LABEL: name: __arm_2d_impl_rgb16_cl_key_1x1_paving_x_mirror_xx
+ ; CHECK: early-clobber renamable $q2 = MVE_VLDRHU16_rq renamable $r0, killed renamable $q1, 0, $noreg, renamable $lr, debug-location !DILocation(line: 83, column: 18, scope: {{.*}}) :: (load (s128), align 1)
+ ; CHECK: renamable $q1, renamable $r8 = MVE_VDDUPu16 killed renamable $r8, 1, 0, $noreg, renamable $lr, undef renamable $q1, debug-location !DILocation(line: 84, column: 22, scope: {{.*}})
+ ; CHECK: MVE_VPTv8i16r 8, renamable $q2, renamable $r11, 1, implicit-def $vpr, debug-location !DILocation(line: 85, column: 17, scope: {{.*}})
+ ; CHECK: renamable $r6 = MVE_VSTRHU16_post killed renamable $q2, killed renamable $r6, 16, 1, killed renamable $vpr, renamable $lr, debug-location !DILocation(line: 86, column: 13, scope: {{.*}}) :: (store (s128) into %ir.pDst.01, align 2)
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.3, debug-location !DILocation(line: 89, column: 9, scope: {{.*}})
+ bb.0.entry:
+ successors: %bb.1(0x50000000), %bb.5(0x30000000)
+ liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r10, $r11
+
+ DBG_VALUE $r0, $noreg, !33, !DIExpression(), debug-location !62
+ DBG_VALUE $r1, $noreg, !34, !DIExpression(), debug-location !62
+ DBG_VALUE $r2, $noreg, !35, !DIExpression(), debug-location !62
+ DBG_VALUE $r3, $noreg, !36, !DIExpression(), debug-location !62
+ frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, $r7, killed $lr, implicit-def $sp, implicit $sp
+ frame-setup CFI_INSTRUCTION def_cfa_offset 20
+ frame-setup CFI_INSTRUCTION offset $lr, -4
+ frame-setup CFI_INSTRUCTION offset $r7, -8
+ frame-setup CFI_INSTRUCTION offset $r6, -12
+ frame-setup CFI_INSTRUCTION offset $r5, -16
+ frame-setup CFI_INSTRUCTION offset $r4, -20
+ $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
+ frame-setup CFI_INSTRUCTION def_cfa $r7, 8
+ $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r10, killed $r11
+ frame-setup CFI_INSTRUCTION offset $r11, -24
+ frame-setup CFI_INSTRUCTION offset $r10, -28
+ frame-setup CFI_INSTRUCTION offset $r9, -32
+ frame-setup CFI_INSTRUCTION offset $r8, -36
+ DBG_VALUE $r7, 0, !37, !DIExpression(DW_OP_plus_uconst, 8), debug-location !62
+ DBG_VALUE $r7, 0, !38, !DIExpression(DW_OP_plus_uconst, 12), debug-location !62
+ early-clobber $sp = t2STR_PRE killed $r3, $sp, -4, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
+ DBG_VALUE $sp, 0, !36, !DIExpression(), debug-location !62
+ DBG_VALUE $sp, 0, !36, !DIExpression(), debug-location !62
+ renamable $r6 = tLDRi $r7, 3, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.1)
+ DBG_VALUE 0, $noreg, !43, !DIExpression(), debug-location !63
+ DBG_VALUE $noreg, $noreg, !40, !DIExpression(DW_OP_LLVM_convert, 16, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), debug-location !62
+ renamable $r3 = t2LDRSHi12 renamable $r6, 2, 14 /* CC::al */, $noreg :: (load (s16) from %ir.iHeight, !tbaa !64)
+ DBG_VALUE $noreg, $noreg, !35, !DIExpression(), debug-location !62
+ DBG_VALUE $noreg, $noreg, !34, !DIExpression(), debug-location !62
+ DBG_VALUE $noreg, $noreg, !33, !DIExpression(), debug-location !62
+ tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr, debug-location !70
+ DBG_VALUE $noreg, $noreg, !39, !DIExpression(), debug-location !62
+ DBG_VALUE $r0, $noreg, !33, !DIExpression(), debug-location !62
+ tBcc %bb.5, 11 /* CC::lt */, killed $cpsr, debug-location !70
+
+ bb.1.for.body.lr.ph:
+ successors: %bb.2(0x80000000)
+ liveins: $r0, $r1, $r2, $r3, $r6
+
+ DBG_VALUE 0, $noreg, !43, !DIExpression(), debug-location !63
+ DBG_VALUE $sp, 0, !36, !DIExpression(), debug-location !62
+ DBG_VALUE $r7, 0, !38, !DIExpression(DW_OP_plus_uconst, 12), debug-location !62
+ DBG_VALUE $r7, 0, !37, !DIExpression(DW_OP_plus_uconst, 8), debug-location !62
+ DBG_VALUE $r0, $noreg, !33, !DIExpression(), debug-location !62
+ renamable $r10 = t2LDRSHi12 killed renamable $r6, 0, 14 /* CC::al */, $noreg :: (load (s16) from %ir.iWidth33, !tbaa !72)
+ renamable $r5 = tLDRi $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.2, align 8)
+ $r6 = tMOVr $r10, 14 /* CC::al */, $noreg, debug-location !70
+ renamable $r5 = t2LDRSHi12 killed renamable $r5, 0, 14 /* CC::al */, $noreg, debug-location !71 :: (load (s16) from %ir.iWidth2, !tbaa !72)
+ DBG_VALUE $r5, $noreg, !40, !DIExpression(), debug-location !62
+ t2CMPri renamable $r10, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr, debug-location !70
+ t2IT 10, 8, implicit-def $itstate, debug-location !70
+ renamable $r6 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r6, implicit killed $itstate, debug-location !70
+ renamable $r6 = t2SUBrr renamable $r10, killed renamable $r6, 14 /* CC::al */, $noreg, $noreg, debug-location !70
+ renamable $r11 = t2LDRi12 $r7, 16, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8)
+ DBG_VALUE $r11, $noreg, !39, !DIExpression(), debug-location !62
+ renamable $r12 = nsw t2SUBri killed renamable $r5, 1, 14 /* CC::al */, $noreg, $noreg
+ renamable $r6, dead $cpsr = tADDi8 killed renamable $r6, 7, 14 /* CC::al */, $noreg, debug-location !70
+ renamable $r5, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $q0, renamable $r12 = MVE_VDDUPu16 killed renamable $r12, 1, 0, $noreg, $noreg, undef renamable $q0, debug-location !62
+ renamable $r9 = nuw nsw t2ADDrs killed renamable $r5, killed renamable $r6, 27, 14 /* CC::al */, $noreg, $noreg, debug-location !70
+ renamable $r4, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+
+ bb.2.for.body (align 4):
+ successors: %bb.3(0x80000000)
+ liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r9, $r10, $r11, $r12
+
+ DBG_VALUE $r11, $noreg, !39, !DIExpression(), debug-location !62
+ DBG_VALUE $sp, 0, !36, !DIExpression(), debug-location !62
+ DBG_VALUE $r7, 0, !38, !DIExpression(DW_OP_plus_uconst, 12), debug-location !62
+ DBG_VALUE $r7, 0, !37, !DIExpression(DW_OP_plus_uconst, 8), debug-location !62
+ DBG_VALUE $r0, $noreg, !33, !DIExpression(), debug-location !62
+ DBG_VALUE $r0, $noreg, !33, !DIExpression(), debug-location !62
+ DBG_VALUE $r2, $noreg, !35, !DIExpression(), debug-location !62
+ DBG_VALUE $r4, $noreg, !43, !DIExpression(), debug-location !63
+ DBG_VALUE $r2, $noreg, !46, !DIExpression(), debug-location !75
+ DBG_VALUE $r0, $noreg, !49, !DIExpression(), debug-location !75
+ DBG_VALUE $r10, $noreg, !50, !DIExpression(), debug-location !75
+ DBG_VALUE $noreg, $noreg, !51, !DIExpression(), debug-location !75
+ DBG_VALUE $noreg, $noreg, !52, !DIExpression(), debug-location !75
+ $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
+ $r5 = tMOVr $r10, 14 /* CC::al */, $noreg
+ $q1 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q1
+ $r8 = tMOVr $r12, 14 /* CC::al */, $noreg
+ renamable $lr = t2DoLoopStartTP renamable $r9, renamable $r10, debug-location !76
+
+ bb.3.do.body (align 4):
+ successors: %bb.3(0x7c000000), %bb.4(0x04000000)
+ liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r10, $r11, $r12
+
+ DBG_VALUE $r0, $noreg, !49, !DIExpression(), debug-location !75
+ DBG_VALUE $r4, $noreg, !43, !DIExpression(), debug-location !63
+ DBG_VALUE $r11, $noreg, !39, !DIExpression(), debug-location !62
+ DBG_VALUE $sp, 0, !36, !DIExpression(), debug-location !62
+ DBG_VALUE $r7, 0, !38, !DIExpression(DW_OP_plus_uconst, 12), debug-location !62
+ DBG_VALUE $r7, 0, !37, !DIExpression(DW_OP_plus_uconst, 8), debug-location !62
+ DBG_VALUE $r2, $noreg, !35, !DIExpression(), debug-location !62
+ DBG_VALUE $r0, $noreg, !33, !DIExpression(), debug-location !62
+ DBG_VALUE $r6, $noreg, !46, !DIExpression(), debug-location !75
+ DBG_VALUE $r5, $noreg, !50, !DIExpression(), debug-location !75
+ DBG_VALUE $r8, $noreg, !51, !DIExpression(), debug-location !75
+ DBG_VALUE $q1, $noreg, !52, !DIExpression(), debug-location !75
+ renamable $vpr = MVE_VCTP16 renamable $r5, 0, $noreg, $noreg, debug-location !77
+ DBG_VALUE $noreg, $noreg, !58, !DIExpression(), debug-location !78
+ MVE_VPST 1, implicit $vpr, debug-location !79
+ early-clobber renamable $q2 = MVE_VLDRHU16_rq renamable $r0, killed renamable $q1, 1, renamable $vpr, renamable $lr, debug-location !79 :: (load (s128), align 1)
+ DBG_VALUE $q2, $noreg, !61, !DIExpression(), debug-location !78
+ renamable $q1, renamable $r8 = MVE_VDDUPu16 killed renamable $r8, 1, 1, renamable $vpr, renamable $lr, undef renamable $q1, debug-location !80
+ DBG_VALUE $noreg, $noreg, !52, !DIExpression(), debug-location !75
+ DBG_VALUE $noreg, $noreg, !51, !DIExpression(), debug-location !75
+ renamable $vpr = MVE_VCMPi16r renamable $q2, renamable $r11, 1, 1, killed renamable $vpr, renamable $lr, debug-location !81
+ DBG_VALUE $noreg, $noreg, !58, !DIExpression(DW_OP_LLVM_convert, 32, DW_ATE_unsigned, DW_OP_LLVM_convert, 16, DW_ATE_unsigned, DW_OP_stack_value), debug-location !78
+ renamable $r6 = MVE_VSTRHU16_post killed renamable $q2, killed renamable $r6, 16, 1, killed renamable $vpr, renamable $lr, debug-location !82 :: (store (s128) into %ir.pDst.01, align 2)
+ DBG_VALUE $r6, $noreg, !46, !DIExpression(), debug-location !75
+ renamable $r5, dead $cpsr = nsw tSUBi8 killed renamable $r5, 8, 14 /* CC::al */, $noreg, debug-location !84
+ DBG_VALUE $r5, $noreg, !50, !DIExpression(), debug-location !75
+ renamable $lr = t2LoopEndDec killed renamable $lr, %bb.3, implicit-def dead $cpsr, debug-location !85
+ tB %bb.4, 14 /* CC::al */, $noreg, debug-location !85
+
+ bb.4.do.end:
+ successors: %bb.5(0x04000000), %bb.2(0x7c000000)
+ liveins: $q0, $r0, $r1, $r2, $r3, $r4, $r9, $r10, $r11, $r12
+
+ DBG_VALUE $r5, $noreg, !50, !DIExpression(), debug-location !75
+ DBG_VALUE $r6, $noreg, !46, !DIExpression(), debug-location !75
+ DBG_VALUE $r0, $noreg, !49, !DIExpression(), debug-location !75
+ DBG_VALUE $r4, $noreg, !43, !DIExpression(), debug-location !63
+ DBG_VALUE $r11, $noreg, !39, !DIExpression(), debug-location !62
+ DBG_VALUE $sp, 0, !36, !DIExpression(), debug-location !62
+ DBG_VALUE $r7, 0, !38, !DIExpression(DW_OP_plus_uconst, 12), debug-location !62
+ DBG_VALUE $r7, 0, !37, !DIExpression(DW_OP_plus_uconst, 8), debug-location !62
+ DBG_VALUE $r2, $noreg, !35, !DIExpression(), debug-location !62
+ DBG_VALUE $r0, $noreg, !33, !DIExpression(), debug-location !62
+ renamable $r6 = tLDRspi $sp, 0, 14 /* CC::al */, $noreg, debug-location !90 :: (load (s32) from %stack.0)
+ renamable $r4, dead $cpsr = nuw nsw tADDi8 killed renamable $r4, 1, 14 /* CC::al */, $noreg, debug-location !91
+ DBG_VALUE $r4, $noreg, !43, !DIExpression(), debug-location !63
+ renamable $r0 = t2ADDrs killed renamable $r0, renamable $r1, 10, 14 /* CC::al */, $noreg, $noreg, debug-location !89
+ DBG_VALUE $r0, $noreg, !33, !DIExpression(), debug-location !62
+ tCMPr renamable $r4, renamable $r3, 14 /* CC::al */, $noreg, implicit-def $cpsr, debug-location !70
+ renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r6, 10, 14 /* CC::al */, $noreg, $noreg, debug-location !90
+ DBG_VALUE $r2, $noreg, !35, !DIExpression(), debug-location !62
+ tBcc %bb.2, 1 /* CC::ne */, killed $cpsr, debug-location !70
+
+ bb.5.for.cond.cleanup:
+ DBG_VALUE $sp, 0, !36, !DIExpression(), debug-location !62
+ DBG_VALUE $r7, 0, !38, !DIExpression(DW_OP_plus_uconst, 12), debug-location !62
+ DBG_VALUE $r7, 0, !37, !DIExpression(DW_OP_plus_uconst, 8), debug-location !62
+ DBG_VALUE $r0, $noreg, !33, !DIExpression(), debug-location !62
+ $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg, debug-location !74
+ $sp = frame-destroy t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r10, def $r11, debug-location !74
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc, debug-location !74
+
+...
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