[PATCH] D109963: [AArch64] Split bitmask immediate of bitwise AND operation

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 updated this revision to Diff 375557.
jaykang10 added a comment.

Fixed a bug.

The destination register class of `AND` register is different with `AND` immediate one. In order to align the register class, the `COPY` MI is added to convert register class as below.

    %1:gpr32 = MOVi32imm 2098176
    %2:gpr32common = ANDWrr %0:gpr32, killed %1:gpr32
  ==>
    %5:gpr32sp = ANDWri %0:gpr32, 1419
    %6:gpr32 = COPY %5:gpr32sp
    %7:gpr32sp = ANDWri %6:gpr32, 725
    %2:gpr32common = COPY %7:gpr32sp


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109963/new/

https://reviews.llvm.org/D109963

Files:
  llvm/lib/Target/AArch64/AArch64.h
  llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
  llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
  llvm/lib/Target/AArch64/CMakeLists.txt
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h
  llvm/test/CodeGen/AArch64/O3-pipeline.ll
  llvm/test/CodeGen/AArch64/aarch64-split-and-bitmask-immediate.ll
  llvm/test/CodeGen/AArch64/unfold-masked-merge-scalar-constmask-innerouter.ll

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