[PATCH] D110524: [AArch64ISelLowering] Avoid duplane in some cases when sve enabled

[David Sherwood via Phabricator via llvm-commits]

david-arm added a comment.

Hi @guopeilin, thanks for making the changes. I'm still a little concerned about the test case though as I'm not sure how reliable it will be over time, especially with the `undef` values present in the code. I did manage to reduce this test case to:

  ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
  ; RUN: llc -mattr=+sve -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s
  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64-unknown-linux-gnu"
  
  define <4 x i32> @test_work_knt_val(<16 x i32>* %arg) {
  entry:
    %0 = load <16 x i32>, <16 x i32>* %arg, align 256
    %shvec = shufflevector <16 x i32> %0, <16 x i32> undef, <4 x i32> <i32 14, i32 14, i32 14, i32 14>
    %1 = add <16 x i32> %0, %0
    store <16 x i32> %1, <16 x i32>* %arg, align 256
    ret <4 x i32> %shvec
  }

I think the problem is that there has to be multiple uses of the loaded value (`%0`) in order for the DAG combine to trigger.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110524/new/

https://reviews.llvm.org/D110524